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Texas Instruments PCM4222EVM, Руководство пользователя

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Texas Instruments PCM4222EVM Скачать руководство пользователя страница 14

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Hardware Configuration

The DIT4192 input serial port supports Left Justified and I

2

S formatted PCM data from the PCM4222

audio serial port. The TDM data formats are not supported by the DIT4192 input serial port. The DITFMT
element on switch SW3 is used to select the proper data format for the DIT4192, and must match the data
format that is selected using the FMT0 and FMT1 elements on switch SW3.

Table 16

summarizes the

operation for and relationship between the DIT4192 and PCM4222 data format switches.

Table 16. DIT4192 Data Format Selection

Switch SW3, FMT1

Switch SW3, FMT0

Switch SW3, DITFMT

Audio Data Format

LO

LO

LO

Left Justified

LO

HI

HI

I

2

S

HI

X

X

TDM formats are not supported

Although one DIT4192 transmitter supports transmission of two-channels of PCM audio data at
sampling/frame rates up to and including 216kHz, it is sometimes desirable to use two DIT4192 devices,
each carrying data for only a single channel (left or right, respectively) at a frame rate equal to one-half the
PCM4222 output sampling rate. This is referred to as Single-Channel, Double Sampling Frequency
transmission in the AES3-2003 standard. The DIT4192 Mono mode is used to implement this form of
transmission.

Mono mode is enabled or disabled using the MONO input (pin 21) of the DIT4192 transmitters. The
DITMONO element on switch SW3 is used to control the MONO pin.

Table 17

demonstrates the operation

of the DITMONO switch.

Table 17. DIT4192 Transmission Mode Configuration

Switch SW3, DITMONO

DIT4192 Transmission Mode

LO

Two-channel

HI

Single-Channel Double Sampling Frequency

The MDAT input (pin 20) of the DIT4192 transmitters is used to select left or right channel for transmission
in Mono mode. The MDAT pin of transmitter U13 is connected to ground, selecting the left input channel.
The MDAT pin of transmitter U14 is connected to VDD, selecting the right input channel. In Mono mode,
the left channel is transmitted from AES3 Output #1 (connectors J7 and J8), while the right channel is
transmitted on AES3 Output #2 (connectors J9 and J10).

When Mono mode is disabled, both the left and right channels are output on both AES3 Output #1 and #2.
This allows for simultaneous balanced and unbalanced transmission of the AES3-encoded output data.

Mono Mode Example: Assume that you are transmitting 192kHz two-channel data using the AES3
transmitters, with a 24.576MHz master clock and the clock dividers set to divide by 128. By simply
enabling Mono mode (setting the DITMONO switch to HI), the transmission converts to Single-Channel,
Double Sampling Frequency mode with an output frame rate equal to 96kHz. There is no need to change
the master clock divider or frequency, because the DIT4192 manages the change in output frame rate
automatically.

PCM4222EVM User's Guide

14

SBAU124 – December 2006

Submit Documentation Feedback

Содержание PCM4222EVM

Страница 1: ...ce 16 List of Figures 1 PCM4222 Functional Block Diagram 3 2 Simplified Block Diagram for the PCM4222EVM Evaluation Module 5 3 Power Supply Jumper Configuration 7 4 PCM4222EVM Schematics Page 1 of 2 17 5 PCM4222EVM Schematics Page 2 of 2 18 List of Tables 1 Absolute Operating Conditions 6 2 Recommended Power Supply Range 7 3 Master Clock Source Selection 9 4 Master Clock Frequencies for Common Out...

Страница 2: ... 15 20 DSD Output Rate Selection 15 21 Modulator Data Port Header Pin Configuration 16 22 Multi Bit Modulator MBM Output Mode Configuration 16 23 Bill of Materials 19 2 PCM4222EVM User s Guide SBAU124 December 2006 Submit Documentation Feedback ...

Страница 3: ...ntroduction The PCM4222EVM evaluation module from Texas Instruments provides a convenient platform for testing the PCM4222 a high performance stereo audio analog to digital A D converter integrated circuit Figure 1 shows a block diagram of the PCM4222 device Refer to the PCM4222 product datasheet for additional information and details regarding this product The PCM4222EVM evaluation module include...

Страница 4: ...bit clock for the DSD output A buffered modulator output port header provides access to the PCM4222 6 bit modulator data outputs and clocks Support for onboard or external clock generation Two onboard crystal oscillators provide support for common audio sampling rates including 44 1kHz 48kHz 88 2kHz 96kHz 176 4kHz and 192kHz Light emitting diode LED overflow indicators for the left and right audio...

Страница 5: ...DIT J3 Introduction Figure 2 shows a simplified block diagram for the PCM4222EVM circuit functions The blocks labeled FDA are the OPA1632 fully differential amplifier input circuits U4 and U5 The blocks labeled DIT are the DIT4192 digital audio interface transmitters U13 and U14 Two transmitters are required to support AES3 Single Channel Double Sampling Frequency applications Figure 2 Simplified ...

Страница 6: ...D handling procedures may result in damage to EVM components CAUTION Exceeding the absolute operating conditions may result in improper operation or damage to the evaluation module and or the equipment connected to it Table 1 summarizes the critical data points for the PCM4222EVM absolute operating conditions Table 1 Absolute Operating Conditions PARAMETER MIN MAX UNIT Analog Power Supplies 15V 0 ...

Страница 7: ...e internal analog circuitry Designated as VCC this supply may be derived from the 15V analog power supply using an onboard linear regulator circuit comprised of U23 and the associated components The regulator circuit is protected in the event that a short circuit occurs between the 15V supply and ground The EVM also supports an external 4 0V power supply which may be connected at the EXT VCC termi...

Страница 8: ...rd PCB layout supports limited board stuff options for experimentation The full scale input voltage for the input buffer circuit is approximately 4 2VRMS or 14 6845dBu differential given a nominal VCC supply of 4 0V for the PCM4222 and a source impedance of 40Ω Due to the full scale input voltage varying slightly from one PCM4222 device to another the full scale input swing should be calibrated fo...

Страница 9: ...age regulator U22 and is tolerant to 5V input logic levels The maximum external master clock frequency is 27 648MHz Table 3 summarizes the master clock source selection using switch SW6 Note that the user should not enable oscillators X1 and X2 simultaneously because it will result in output contention and improper operation Table 4 lists the master clock rate requirements for commonly used digita...

Страница 10: ...es the operation of the PCMEN element on switch SW1 When the PCM output is disabled the DATA pin 32 output is forced low If the PCM4222 is set to Master mode the BCK pin 33 and LRCK pin 34 clock outputs are also forced low when the PCM output is disabled Table 5 PCM Output Mode Configuration Switch SW1 PCMEN PCM Output Mode LO PCM Output Disabled HI PCM Output Enabled The PCM output operates in on...

Страница 11: ...ns sourced from an external audio serial port master such as a digital signal processor serial port a serial timing generator or a programmable logic device Once again the LRCK clock rate is always equal to the desired output sampling rate The BCK clock rate depends on the audio data format selected Refer to the PCM4222 datasheet for audio serial port operational details The Slave Master mode oper...

Страница 12: ...allows the device to output 20 18 or 16 bits of audio data when needed The output word length is determined by the OWL0 and OWL1 inputs pins 42 and 41 respectively These pins are controlled by the OWL0 and OWL1 element switch SW3 Table 11 summarizes the operation of the OWL0 and OWL1 switches Table 11 PCM Output Word Length Selection Switch SW3 OWL1 Switch SW3 OWL0 Output Data Word Length LO LO 24...

Страница 13: ...fer U11 is used to enable disable the clock and data flow from the PCM4222 to the DIT4192 devices The DIT switch on SW3 is used to enable or disable the buffer Table 14 summarizes the DIT switch settings Table 14 DIT4192 Serial Data and Clock Enable Operation Switch SW3 DIT DIT4192 Input Data Clock Enable LO Enabled Data and clocks flow from the PCM4222 to U13 and U14 Disabled The tri state buffer...

Страница 14: ...TMONO element on switch SW3 is used to control the MONO pin Table 17 demonstrates the operation of the DITMONO switch Table 17 DIT4192 Transmission Mode Configuration Switch SW3 DITMONO DIT4192 Transmission Mode LO Two channel HI Single Channel Double Sampling Frequency The MDAT input pin 20 of the DIT4192 transmitters is used to select left or right channel for transmission in Mono mode The MDAT ...

Страница 15: ...ed or disabled using the DSDEN input pin 22 This input is controlled via the DSDEN element on switch SW1 Table 19 summarizes the operation of this switch When the DSD output is disabled DSDCLK pin 27 DSDL pin 28 and DSDR pin 29 are forced low Table 19 DSD Output Mode Configuration Switch SW1 DSDEN DSD Output Mode LO Disabled HI Enabled The DSD output data rate may be set to 64x or 128x the base PC...

Страница 16: ...modulator data and clock outputs The PCMEN input pin 16 must be set to the LO position when the MBM output is enabled When MBM mode is disabled all data and clock outputs associated with the interface are driven low assumes PCM and DSD modes are also disabled Table 22 Multi Bit Modulator MBM Output Mode Configuration Switch SW1 MODEN Switch SW1 PCMEN Switch SW1 DSDEN MBM Output Mode LO X X Disable...

Страница 17: ...15 SN74ALVC245PW VDD C29 0 1uF RN14 100 RN15 100 VDD C19 0 1uF C25 0 1uF C24 0 1uF 15V C50 22uF C22 0 1uF R1 0 R9 560 R2 0 R10 560 C10 0 1uF C5 1nF C52 NI 8 2 1 3 6 4 5 VOCM 7 _ _ EN U5 OPA1632DGN R20 40 2 R19 40 2 R3 0 R4 0 C61 2 7nF C6 1nF C53 NI 1 2 JMP4 C49 22uF R13 270 15V R14 270 TP5 VINR TP6 VINR 2 3 6 7 4 1 8 U3 OPA227UA C14 0 1uF C13 0 1uF 15V 15V C1 NI C2 NI C15 0 1uF R23 1K C26 0 1uF C1...

Страница 18: ...SS 1 COPY C 2 L 3 CLK1 4 CLK0 5 MCLK 6 VIO 7 DGND 8 FMT0 9 FMT1 10 SCLK 11 SYNC 12 SDATA 13 M S 14 MODE 28 U 27 V 26 BLS 25 BLSM 24 EMPH 23 AUDIO 22 MONO 21 MDAT 20 VDD 19 TX 18 TX 17 DGND 16 RST 15 U14 DIT4192IPW VDD C79 10uF C80 10uF C38 0 1uF C39 0 1uF C46 0 1uF C82 10uF 5V 5V C40 0 1uF R29 110 C47 0 1uF R30 110 REG J8 AES3 OUTPUT 1 75 ohms J10 AES3 OUTPUT 2 75 ohms LRCK BCK SCKI DATA C45 0 1uF...

Страница 19: ...emet T494B106K016AT 10µF 10 16WV Size B Chip Capacitor Solid Tantalum 22µF 12 NI 22µF C48 C51 Kemet T491D226K025AT 10 25WV Size D C63 C65 C67 Chip Capacitor Polymer Tantalum 13 5 100µF Kemet T520B107M006ATE070 C69 100µF 20 6 3WV Size B Chip Capacitor Polymer Tantalum 14 NI 100µF C64 C68 Kemet T520B107M006ATE070 100µF 20 6 3WV Size B 15 NI C11 C23 Item Removed from Design N A N A Capacitor Alum Ele...

Страница 20: ... CTS 742C163103JP RN13 RN16 16 Terminal 8 Resistors RN11 RN14 42 NI Item Removed from Design N A N A RN15 DIP Switch 10 Element Half Pitch 43 2 SW1 SW3 ITT C K Switch TDA10H0SB1 Surface Mount Tape Sealed DIP Switch 2 Element Half Pitch 44 1 SW2 ITT C K Switch TDA02H0SB1 Surface Mount Tape Sealed Momentary Tact Switch SMT w o 45 2 SW4 SW5 Omron B3S 1000 Ground Terminal DIP Switch 4 Element Half Pit...

Страница 21: ...tor 60 1 U23 Linear Voltage Regulator Adjustable LM317MSTT3G or or National LM317EMP Semiconductor 3 3V Surface Mount Clock 61 1 X1 Oscillator CMOS Output with Active Pletronics SM7745HSV 22 5792M High Enable 22 5792MHz 50ppm 3 3V Surface Mount Clock 62 1 X2 Oscillator CMOS Output with Active Pletronics SM7745HSV 24 576M High Enable 24 576MHz 50ppm 63 6 Shorting Blocks Samtec SNT 100 BK T H 64 4 S...

Страница 22: ...uction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES TI currently deals with a variety of customers for products and therefore our arrangement with the user i...

Страница 23: ...siness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necess...

Страница 24: ...мые продукты мы предоставляем гарантию Осуществляем поставки продукции под контролем ВП МО РФ на предприятия военно промышленного комплекса России а также работаем в рамках 275 ФЗ с открытием отдельных счетов в уполномоченном банке Система менеджмента качества компании соответствует требованиям ГОСТ ISO 9001 Минимальные сроки поставки гибкие цены неограниченный ассортимент и индивидуальный подход ...

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