Texas Instruments PCM1840EVM, Руководство пользователя, Страница: 4 / 21

Hardware Configuration
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4 SBAU345 – March 2020
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PCM1840 Evaluation Module
Table 1. PCM1840 EVM Headers and Jumpers (continued)
Designator Function
J16 Microphone OUT– to ADC IN1M
J17 MDO select
J18 MD1 select
J19 Connect MCLK to MD1
J20 FMT0 select
J21 FMT1 select
Table 2. PCM1840 Hardware Controllable Settings
MD0 Modes
MD0 MSZ (0 = Slave, 1 = Master) MDO Functional Mode
0 0 Linear phase filter
0 1 MCLK = 256 × Fs
1 0 Low latency filter
1 1 MCLK = 512 × Fs
MD1 Modes
MD1 MSZ (0 = Slave, 1 = Master) MD1 Functional Mode
0 0 DRE disabled
0 1 MCLK input
1 0 DRE enabled
1 1 MCLK input
Audio Output Data Format
FMT0 FMT1 Data Format
0 0 4 channel TDM
0 1 2 channel TDM
1 0 2 channel left-justified
1 1 2 channel I2S
All hardware pins are tied low by default, placing the device in slave mode with a linear phase filter, DRE
disabled, and 4-channel TDM audio output.
For more information on the operating modes of the PCM1840 device, see the PCM1840 Quad Channel,
32-Bit, 192-kHz, Burr-Brown™ Audio ADC Data Sheet .