Texas Instruments OMAP36 Series, Техническое справочное руководство

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IVA2.2 Subsystem Register Manual
Table 5-372. TPCC_IEVAL_Rn
Address Offset (0x200*n) n = 0 to 7
Physical address 0x01C0 2078 + (0x200*n) n Instance IVA2.2 TPCC
= 0 to 7
Description Interrupt Eval Register
Type W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
SET
EVAL
Bits Field Name Description Type Reset
31:2 Reserved Write 0s for future compatibility. W 0x00000000
1 SET Interrupt Set: W 0
CPU write of 1 to the SETn bit causes the tpcc_intN output signal to
be pulsed egardless of state of interrupts enable (IERn) and status
(IPRn).
CPU write of 0 has no effect.
0 EVAL Interrupt Evaluate: W 0
CPU write of 1 to the EVALn bit causes the tpcc_intN output signal
to be pulsed if any enabled interrupts (IERn) are still pending
(IPRn).
CPU write of 0 has no effect.
Table 5-373. Register Call Summary for Register TPCC_IEVAL_Rn
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [0]
Table 5-374. TPCC_QER_Rn
Address Offset (0x200*n) n = 0 to 7
Physical address 0x01C0 2080 + (0x200*n) n Instance IVA2.2 TPCC
= 0 to 7
Description QDMA Event Register:
If QER.En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to
the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En
bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a
1 to the QSECR.En
bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location
and QEER register is set, then the corresponding bit in the QDMA Event Missed Register is set.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
E7 E6 E5 E4 E3 E2 E1 E0
Bits Field Name Description Type Reset
31:8 Reserved Read returns 0. R 0x000000
7 E7 Event #7 R 0
6 E6 Event #6 R 0
5 E5 Event #5 R 0
4 E4 Event #4 R 0
3 E3 Event #3 R 0
2 E2 Event #2 R 0
1 E1 Event #1 R 0
0 E0 Event #0 R 0
945 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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