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IVA2.2 Subsystem Basic Programming Model
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5.4.8.2 Event Combined Programming Sequence
In addition to generating a combined interrupt based on programmable event combinations, the event
combiner provides a masked view of the event flag registers. By reading the masked event flag
(IVA_IC.
MEVTFLAGi where i = {0 to 3}) registers, the DSP CPU sees only the event flags pertaining to
the corresponding combined event (EVTx with x = {0, 1, 2, 3}).
When servicing a combined interrupt, perform the following steps:
1. Read the IVA_IC. MEVTFLAGi register corresponding to the combined event EVTx (where i = {0 to 3}).
2. Check the pending events.
3. Write the value of the IVA_IC.
MEVTFLAGi register into the IVA_IC.EVTCLRx register (where i = {0 to
3}).
4. Service the received interrupts.
5. Repeat steps 1 through 4 until IVA_IC.
MEVTFLAGi = 0x0 (where i = {0 to 3}).
This clears only those events combined on EVTx. Any events masked in the IVA_IC. EVTMASKi register
(where i = {0 to 3}) do not need to be cleared if set in the IVA_IC. EVTFLAGi register (where i = {0 to 3})
(they can generate an exception or are used as event outputs).
Before returning, the DSP CPU should repeat steps 1 through 4 until no pending events are found. This
ensures that any events received during the ISR are captured. If an event EVTx is received at the same
time that its flag is being cleared in the IVA_IC.
EVTCLRi register (where i = {0 to 3}), it does not clear.
Repeating steps 1 through 4 ensures that no events are missed.
5.4.8.3 Event <-> Interrupt Mapping Programming Sequence
The INTC allows programming independently which of the 128 inputs events is mapped to each DSP CPU
interrupt by writing the event number in the bit field corresponding to the CPU interrupt in the IC.
INTMUXj
registers (where j = {1 to 3}).
Example:
/* ---------------------------------------------------- */
/*evtTable has the 12 evt <-> CPU interrupt mapping */
/* ---------------------------------------------------- */
evtTable[0] = 55; // Mailbox event highest priority
evtTable[1] = 61; // McBSP1TX event
[...]
evtTable[11] = 29; // EDMA3 gbl completion event lowest priority
for(I=0; i<12; I++) {// for each CPU maskeable interrupt
INTMUX(I >> 2 + 1) |= (evtTable[i] & 0x7F) << ((I & 0x3) << 3);
}
5.4.8.4 Interrupt Exception Programming Sequence
The INTC can generate a system event (INTERR) that is internally routed to system event input EVT96.
This event is generated when a DSP CPU interrupt is dropped (that is, when a DSP CPU interrupt is
received while the interrupt flag is already set in the DSP CPU).
This can inform the user of possible problems in the software code, such as whether interrupts were
disabled for an extended period of time, or whether pipelined (noninterruptible) code sections were too
long.
NOTE: Because the interrupt drop detection logic is in the CPU, only interrupts sourced from a
single system event can be detected. The dropping of individual combined events is not
possible, although dropping the output of an event combiner is possible. Only the first
dropped interrupt detected is reported by the INTERR event.
The IVA_IC. INTXSTAT register holds the ID of the CPU interrupt and the system event number of the
dropped event. By setting the IVA_IC. INTXCLR [0] CLEAR bit to 1, the software user resets the
IVA_IC. INTXSTAT register to 0.
782 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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