Texas Instruments OMAP36 Series, Техническое справочное руководство

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Device
System
clock
DMA
requests
Interrupts
IVA2.2 subsystem
SYSC
Internal
clocks
(CD0,
CD1,
CD2)
Local
interconnect
management
48
External
peripherals
IRQ
WUGEN
13
EDMA
IRQ
20
EDMA
requests
32
4x64
64
Local interconnect
EDMA
64 64
MMU
master port
DSP megamodule
32/1
(see note)
64/7 (see note)
L3 interconnect L4 interconnect
Slave
port
32
32
CPU IRQ
VIDEO_IRQ
32
256
256
256
Arb
Memory
mapped
and
cache
ROM
8x32
256
L2 L1D RAM L1P RAM
Memory
mapped
and
cache
Memory
mapped
and
cache
256
iLF
iVLCD
iME
SEQ
SL2IF
32
32
32 256
256
32
32
Config
IVA2.2 boot
configuration
VIDEO
SYSC
iva2-007
Public Version
IVA2.2 Subsystem Functional Description
www.ti.com
5.3 IVA2.2 Subsystem Functional Description
The IVA2.2 subsystem is composed of a DSP megamodule coupled with several submodules that enable
its integration in the device architecture. The IVA2.2 subsystem provides one slave port and one master
port; both ports are connected to the L3 interconnect.
Figure 5-7 is a block diagram of the IVA2.2 subsystem.
Figure 5-7. IVA2.2 Subsystem Block Diagram
NOTE: This indicates the number of threads for IVA2.2 master/slave port interrupts. For details, see Chapter 9 ,
Interconnect.
5.3.1 DSP Megamodule
The C64x+ DSP megamodule is a class of derivative sections of the generalized embedded megamodule.
DSP megamodule is a hardware-configurable megamodule module that comprises a version of the
C64x+, an L1 program memory controller (PMC), an L1 data memory controller (DMC), a unified memory
controller (UMC), an extended memory controller (EMC), an INTC, and a power-down controller (PDC).
Figure 5-8 is a block diagram of the DSP megamodule.
706 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated