Texas Instruments OMAP36 Series, Техническое справочное руководство

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PRCM Register Manual
Bits Field Name Description Type Reset
31:2 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
1 EN_MPU MPU domain dependency RW 0x0
0x0: SGX domain sleep dependency with MPU domain is
disabled.
0x1: SGX domain sleep dependency with MPU domain is
enabled.
0 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0
Table 3-170. Register Call Summary for Register CM_SLEEPDEP_SGX
PRCM Basic Programming Model
• CM_SLEEPDEP_ <domain_name> (Sleep Dependency Control Register) : [0]
PRCM Register Manual
• SGX_CM Register Summary : [1]
Table 3-171. CM_CLKSTCTRL_SGX
Address Offset 0x0000 0048
Physical Address 0x4800 4B48 Instance SGX_CM
Description This register enables the domain power state transition. It controls the HW supervised domain power
state transition between ACTIVE and INACTIVE states.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
CLKTRCTRL_SGX
Bits Field Name Description Type Reset
31:2 RESERVED Write 0s for future compatibility. Reads returns 0. R 0x00000000
1:0 CLKTRCTRL_SGX Controls the clock state transition of the SGX clock RW 0x0
domain.
0x0: Automatic transition is disabled
0x1: Start a software supervised sleep transition on the
domain
0x2: Start a software supervised wake-up transition on
the domain
0x3: Automatic transition is enabled. Transition is
supervised by the hardware.
Table 3-172. Register Call Summary for Register CM_CLKSTCTRL_SGX
PRCM Functional Description
• Device Wake-Up Events : [0] [1] [2]
PRCM Basic Programming Model
• CM_CLKSTCTRL_ <domain_name> (Clock State Control Register) : [3]
PRCM Register Manual
• SGX_CM Register Summary : [4]
491 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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