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High-Speed USB Host Subsystem
Bits
Field Name
Description
Type
Reset
0x2: 256 elements (1024 bytes), for resource-constrained
environments
0x3: Reserved
1
HCR
Host Controller Reset
W
0
This control bit is used by software to reset the host
controller. Write
0x1: Reset the host controller, the PCI configuration
registers are not affected by this reset and all operational
registers are set to their initial values.
This bit is set to 0 by the host controller when the reset
process is complete.
0
RS
Run/stop
RW
0
0x1: Run, the host controller proceeds with execution of
the schedule. The host controller continues execution as
long as this bit is set to 1.
0x0: Stop, the host controller completes the current and
any actively pipelined transactions on the USB and then
halts.
Table 22-219. Register Call Summary for Register USBCMD
High-Speed USB Host Subsystem
•
High-Speed USB Host Subsystem Register Summary
•
High-Speed USB Host Subsystem Register Description
:
Table 22-220. USBSTS
Address Offset
0x0000 0014
Physical Address
0x4806 4814
Instance
EHCI
Description
USB status
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
RESERVED
IAA
FLR
ASS
PSS
HSE
REC
PCD
HCH
USBI
USBEI
Bits
Field Name
Description
Type
Reset
31:16
RESERVED
Reserved
R
0x0000
15
ASS
Asynchronous Schedule Status
R
0
The bit reports the current real status of the
asynchronous schedule.
0x0: The status of the asynchronous schedule is
disabled.
0x1: The status of the asynchronous schedule is enabled.
14
PSS
Periodic Schedule Status
R
0
The bit reports the current real status of the periodic
schedule.
0x0: The status of the periodic schedule is disabled.
0x1: The status of the periodic schedule is enabled.
13
REC
Reclamation
R
0
It is used to detect an empty asynchronous schedule.
12
HCH
Host Controller Halted
R
1
This bit is a 0 whenever the USBHOST.
3349
SWPU177N – December 2009 – Revised November 2010
High-Speed USB Host Subsystem and High-Speed USB OTG Controller
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...