Texas Instruments OMAP36 Series, Техническое справочное руководство

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A2
CLK (R/X)
D(R/X)
FS(R/X)
A1 B7 B6 B5 B4 B3 B2 B1 B0 A0
C7 C6
C5
mcbsp-027
Public Version
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McBSP Functional Description
Unlike other serial port interrupt modes, this mode can operate while the associated portion of the serial
port is in reset (such as activating receive interrupt when the receiver is in reset). In this case,
McBSPi.
MCBSPLP_PCR_REG [0] FSRM bit/McBSPi. MCBSPLP_PCR_REG [1] FSXM bit and
McBSPi. MCBSPLP_PCR_REG [2] FSRP bit/McBSPi. MCBSPLP_PCR_REG [3] FSXP bit still select the
appropriate source and polarity of frame synchronization. Thus, even when the serial port is in the reset
state, these signals are synchronized to the interface clock (McBSPi_ICLK) and then sent to the
MPU/IVA2.2 subsystem in the form of receive interrupt and transmit interrupt at the point where they feed
the receiver and transmitter of the serial port. Consequently, a new frame-synchronization pulse can be
detected, and then, the MPU/IVA2.2 subsystem can take the serial port out of reset safely.
21.4.2.3.5 Ignoring Frame-Synchronization Pulses
The McBSP module ignores transmit and/or receive frame-synchronization pulses if the frame transfer
was started by a previous frame-synchronization pulse (unexpected frame-synchronization pulses). The
McBSP module does not support features like retransmit or re-receive of an erroneous frame or word. The
receiver or transmitter ignores frame-synchronization pulses until the desired frame length or number of
words is reached. For more details on unexpected frame-synchronization pulses, see
Section 21.4.4.3 , or
Section 21.4.4.6
21.4.2.3.6 Frame Frequency
The frame frequency is determined by the period between frame-synchronization pulses and is defined as
shown in the following equation:
Frame frequency = Clock frequency/(Number of clock cycles between two rising edges [or falling edges] of
two consecutive frame synchronization pulses)
The frame frequency can be increased by decreasing the time between frame-synchronization pulses
(limited only by the number of bits per frame). As the frame transmit frequency increases, the inactivity
period between the data packets for adjacent transfers decreases to zero.
21.4.2.3.7 Maximum Frame Frequency
The minimum number of clock cycles between frame synchronization pulses is equal to the number of bits
transferred per frame. The maximum frame frequency is defined as shown in the following equation:
Maximum frame frequency = clock frequency/Number of bits per frame
Figure 21-28 below shows the McBSP operating at maximum packet frequency. At maximum packet
frequency, the data bits in consecutive packets are transmitted contiguously with no inactivity between
bits.
Figure 21-28. McBSP Operating at Maximum Packet Frequency
If there is a 1–bit data delay as shown in Figure 21-28 , the frame-synchronization pulse overlaps the last
bit transmitted in the previous frame. Effectively, this permits a continuous stream of data, back-to-back
transfers.
NOTE: For McBSPi. MCBSPLP_XCR2_REG [1:0] XDATDLY = 0x0 (0-bit data delay), the first bit of
data is transmitted asynchronously to the internal transmit clock signal (CLKX_int). For more
details, see
Section 21.5.1.6.2.2.5 .
3097 SWPU177N – December 2009 – Revised November 2010 Multi-Channel Buffered Serial Port
Copyright © 2009–2010, Texas Instruments Incorporated