Texas Instruments OMAP36 Series, Техническое справочное руководство

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UART/IrDA/CIR Functional Description
19.4.4.2.3.5 Store and Controlled Transmission
In store and controlled transmission (SCT) mode, the MPU starts writing data to the TX FIFO. Then, after
writing a part of a frame (for a bigger frame) or a whole frame (a small frame; that is, a supervisory frame),
the MPU writes 1 to the UART3.
ACREG_REG [2] SCTX_EN bit (deferred TX start) to start transmission.
SCT mode is enabled by setting the UART3. MDR1_REG [5] SCT bit to 1. This transmission method is
different from the normal mode, in which data transmission starts immediately after data is written to the
TX FIFO. SCT mode is useful for sending short frames without TX underrun.
19.4.4.2.3.6 Error Detection
When the UART3. LSR_REG register is read, the UART3. LSR_REG [4:2] field reflects the error bits [FL,
CRC, ABORT] of the frame at the top of the STATUS FIFO (the next frame status to be read).
The error is triggered by an interrupt (see Table 19-35 for IrDA mode interrupts). STATUS FIFO must be
read until empty (a maximum of eight reads is required).
19.4.4.2.3.7 Underrun During Transmission
Underrun during transmission occurs when the TX FIFO is empty before the end of the frame is
transmitted. When underrun occurs, the device closes the frame with end flags but attaches an incorrect
CRC value. The receiving device detects a CRC error and discards the frame; it can then ask for a
retransmission.
Underrun also causes an internal flag to be set, which disables additional transmissions. Before the next
frame can be transmitted, the system (MPU) must:
•
Reset the TX FIFO.
• Read the UART3. RESUME_REG register (which clears the internal flag).
This functionality can be disabled by the UART3. ACREG_REG [4] DIS_TX_UNDERRUN bit, compensated
by the extension of the stop bit in transmission if the TX FIFO is empty.
19.4.4.2.3.8 Overrun During Receive
Overrun during receive for the IrDA mode has the same functionality as that for the UART mode (see
Section 19.4.4.1.3.6 , Overrun During Receive).
19.4.4.2.3.9 Status FIFO
In IrDA modes, a status FIFO records the received frame status. When a complete frame is received, the
length of the frame and the error bits associated with the frame are written to the status FIFO.
Reading UART3. SFREGH_REG [3:0] (MSB) and UART3. SFREGL_REG [3:0] (LSB) obtains the frame
length. The frame error status is read in the UART3. SFLSR_REG register. Reading the
UART3. SFLSR_REG register increments the status FIFO read pointer. The status FIFO is eight entries
deep and, therefore, can hold the status of eight frames.
The MPU uses the frame-length information to locate the frame boundary in the received frame data. The
MPU can screen bad frames using the error status information and can later request the sender to resend
only the bad frames.
This status FIFO can be used effectively in DMA mode because the MPU must be interrupted only when
the programmed status FIFO trigger level is reached, not each time a frame is received.
19.4.4.2.4 SIR Mode DATA Formatting
This section provides specific instructions for SIR mode programming.
19.4.4.2.4.1 Abort Sequence
When the transmitter prematurely closes a frame, it sends the following sequence to abort: 0x7DC1. The
abort pattern closes the frame without a CRC field or an ending flag.
2913 SWPU177N – December 2009 – Revised November 2010 UART/IrDA/CIR
Copyright © 2009–2010, Texas Instruments Incorporated