Texas Instruments OMAP36 Series, Техническое справочное руководство

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HS I
2
C Register Manual
Bits Field Name Description Type Reset
15 RDMA_EN Receive DMA channel enable RW 0
0x0: Receive DMA channel disabled
0x1: Receive DMA channel enabled
14 RXFIFO_CLR Receive FIFO clear RW 0
0x0: Normal mode
0x1: Rx FIFO is reset
13:8 RTRSH Threshold value for FIFO buffer in RX mode is equal to RW 0x00
RTRSH + 1.
7 XDMA_EN Transmit DMA channel enable RW 0
0x0: Transmit DMA channel disabled
0x1: Transmit DMA channel enabled
6 TXFIFO_CLR Transmit FIFO clear RW 0
0x0: Normal mode
0x1: Tx FIFO is reset
5:0 XTRSH Threshold value for FIFO buffer in TX mode is equal to RW 0x00
XTRSH + 1.
Table 17-28. Register Call Summary for Register I2C_BUF
HS I2C Integration
• HS I2C Power Management : [0] [1]
• HS I2C Interrupt Requests : [2] [3] [4] [5] [6] [7] [8] [9]
HS I2C Functional Description
• HS I2C Receive Mode in I2C Mode : [10]
• HS I2C FIFO Interrupt Mode Operation : [11] [12] [13] [14] [15] [16] [17] [18]
• HS I2C FIFO Polling Mode Operation : [19] [20]
• HS I2C FIFO DMA Mode Operation (I2C Mode Only) : [21] [22] [23] [24] [25]
• HS I2C Draining Feature (I2C Mode Only) : [26] [27] [28] [29] [30] [31] [32] [33]
• HS I2C Write and Read Operations in SCCB Mode : [34] [35]
HS I2C Basic Programming Model
• HS I2C Main Program (I2C Mode) : [36] [37] [38] [39] [40] [41] [42] [43] [44]
• HS I2C Programming Flow Diagrams (I2C Mode) : [45] [46]
• HS I2C Main Program (SCCB Mode) : [47] [48] [49] [50]
HS I2C Register Manual
• HS I2C Register Summary : [51]
• HS I2C Register Summary : [52] [53]
Table 17-29. I2C_CNT
Address Offset 0x18
Physical Address 0x4806 0018 Instance I2C3
0x4807 0018 I2C1
0x4807 2018 I2C2
Description This read/write register is used to control the numbers of bytes in the I2C data payload.
Type RW
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCOUNT
Bits Field Name Description Type Reset
15:0 DCOUNT Data count RW 0x0000
Note: Because the transfer length for DCOUNT=0x0000
is 65536, the module does not allow the initiation of
zero-data-byte transfers..
2827 SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
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