Texas Instruments OMAP36 Series, Техническое справочное руководство

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HS I
2
C Integration
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Table 17-6. HS I
2
C Wake-Up Events (continued)
Wake-Up Supported Enable/Disable Bit
(1)
Event Generated When:
Event Name Configuration
Mode
GC event I
2
C mode only I2Ci. I2C_WE [5] GC_WE A general call is received on the I
2
C bus.
STC event
(2)
I
2
C mode only I2Ci. I2C_WE [6] STC_WE A start (S) condition is detected on the I
2
C bus.
(3)
BF event I
2
C and SCCB I2Ci. I2C_WE [8] BF_WE The bus is free and the LH can initiate its own transfer.
modes
AAS event I
2
C mode only I2Ci. I2C_WE [9] AAS_WE An external master I
2
C device addresses the module of the
device to inform the LH that it can check which of its own
addresses was used by the external master I
2
C device to
access the module of the device.
ROVR event I
2
C receive mode I2Ci. I2C_WE [10] ROVR_WE Overrunning and draining while receiving.
only
XUDF event I
2
C transmit mode I2Ci. I2C_WE [11] XUDF_WE Transmitting and receiving an underflow event during the
only transmission.
RDR event I
2
C receive mode I2Ci. I2C_WE [13] RDR_WE The module, configured as a receiver, has detected a stop (P)
only condition on the I
2
C bus and the RX FIFO threshold
(I2Ci. I2C_BUF [13:8] RTRSH bit field value + 1) is not reached
and the RX FIFO is not empty. This allows the module to
inform the LH that it can check the amount of data to be
transferred from the RX FIFO.
XDR event I
2
C master transmit I2Ci. I2C_WE [14] XDR_WE The TXFIFO level is below the threshold (I2Ci. I2C_BUF [5:0]
mode only XTRSH bit field value + 1) and the amount of data left to be
transferred is less than this threshold. This allows the module
to inform the LH that it can check the amount of data to be
written to the TX FIFO.
(2)
Wake-up event asynchronously detected.
(3)
This event must not be enabled if the functional clock cannot be disabled.
NOTE: With the exception of the STC event, the functional clock must be active for wake-up event
detection to occur. The HS I2C4 has no wake-up capability.
17.3.1.3 HS I
2
C Resets
17.3.1.3.1 HS I
2
C Hardware Reset
The three HS I
2
C controllers receive their reset signal CORE_RST (the reset signal of the CORE power
domain) from the PRCM module.
The HS I2C4 gets its reset signal PRM_RSTPWRON from the reset manager in the PRCM module.
17.3.1.3.2 HS I
2
C Software Reset
Each HS I
2
C controller supports the software reset by accessing the I2Ci. I2C_SYSC [1] SRST bit (1: reset;
0: normal mode).
The software reset status can be checked by accessing the I2Ci. I2C_SYSS [0] RDONE bit (1: reset is
done; 0: reset is ongoing).
To do a software reset, the following steps must be done:
1. Ensure that the module is disabled (clear the I2Ci. I2C_CON [15] I2C_EN bit to 0).
2. Set the I2Ci. I2C_SYSC [1] SRST bit to 1.
3. Enable the module by setting I2Ci. I2C_CON [15] I2C_EN bit to 1.
4. Check the I2Ci. I2C_SYSS [0] RDONE bit until it is set to 1 to indicate the software reset is complete.
2786 SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated