Texas Instruments OMAP36 Series, Техническое справочное руководство

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General-Purpose Timers Register Manual
Table 16-15. GPTIMER9 to GPTIMER11 Register Summary
Register Name Type Register Address Offset Physical Address Physical Address Physical Address
Width (Bits) (GPTIMER9) (GPTIMER10) (GPTIMER11)
TIDR R 32 0x000 0x4904 0000 0x4808 6000 0x4808 8000
TIOCP_CFG RW 32 0x010 0x4904 0010 0x4808 6010 0x4808 8010
TISTAT R 32 0x014 0x4904 0014 0x4808 6014 0x4808 8014
TISR RW 32 0x018 0x4904 0018 0x4808 6018 0x4808 8018
TIER RW 32 0x01C 0x4904 001C 0x4808 601C 0x4808 801C
TWER RW 32 0x020 0x4904 0020 0x4808 6020 0x4808 8020
TCLR RW 32 0x024 0x4904 0024 0x4808 6024 0x4808 8024
TCRR RW 32 0x028 0x4904 0028 0x4808 6028 0x4808 8028
TLDR RW 32 0x02C 0x4904 002C 0x4808 602C 0x4808 802C
TTGR RW 32 0x030 0x4904 0030 0x4808 6030 0x4808 8030
TWPS R 32 0x034 0x4904 0034 0x4808 6034 0x4808 8034
TMAR RW 32 0x038 0x4904 0038 0x4808 6038 0x4808 8038
TCAR1 R 32 0x03C 0x4904 003C 0x4808 603C 0x4808 803C
TSICR RW 32 0x040 0x4904 0040 0x4808 6040 0x4808 8040
TCAR2 R 32 0x044 0x4904 0044 0x4808 6044 0x4808 8044
TPIR RW 32 0x048 - 0x4808 6048 -
TNIR RW 32 0x04C - 0x4808 604C -
TCVR RW 32 0x050 - 0x4808 6050 -
TOCR RW 32 0x054 - 0x4808 6054 -
TOWR RW 32 0x058 - 0x4808 6058 -
16.3.3 GP Timer Register Descriptions
Table 16-16 through Table 16-54 describe the GP timer register bits.
Table 16-16. TIDR
Address Offset 0x000
Physical Address 0x4831 8000 Instance GPT1
0x4903 2000 GPT2
0x4903 4000 GPT3
0x4903 6000 GPT4
0x4903 8000 GPT5
0x4903 A000 GPT6
0x4903 C000 GPT7
0x4903 E000 GPT8
0x4904 0000 GPT9
0x4808 6000 GPT10
0x4808 8000 GPT11
Description This register contains the IP revision code.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved TID_REV
Bits Field Name Description Type Reset
31:8 Reserved Reads return 0. R 0x000000
7:0 TID_REV IP revision R See
(1)
(1)
TI internal data
2727 SWPU177N – December 2009 – Revised November 2010 Timers
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