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SDRAM Controller (SDRC) Subsystem
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Intra-class arbitration: A first level of arbitration is done in parallel within each class between the
different thread groups (request FIFOs).
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Interclass arbitration: A second level of arbitration is done among the three winners of the in-class
arbitration.
10.2.4.1.2.1 Arbitration Policy Within a Burst and at a Burst Boundary
Arbitration is performed on the transaction boundary. The transaction can be either a single transaction or
a burst transaction.
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Within a burst, if the thread cannot provide the subsequent request of the burst, a mechanism provides
a wait for one idle cycle before moving the arbitration grant to the next thread. If only one idle cycle
appears on one thread, an arbitration grant must not move (the next request served must be from the
same thread). One idle cycle is then inserted in the SDRC request path.
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If the thread still cannot provide the request in the next cycle, the slot can be awarded to another
initiator to avoid locking the SDRAM resource, if a thread cannot supply a subsequent request within
the burst. In this case, there must not be a second idle cycle insertion in the SDRC request path. A
burst with fewer than two idle cycles cannot be interrupted by a higher priority request.
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On burst boundary, the arbitration does not wait one idle cycle before moving the arbitration grant. As
soon as the thread cannot request one transaction at a burst boundary, the arbitration grant can move
to the next thread.
This is also valid within the ExtendedGrant and NOfServices windows; as soon as the thread cannot
request a transaction, the arbitration grant can move to the next thread. For more information, see the
following descriptions of the ExtendedGrant and NOfServices features.
10.2.4.1.2.2 Burst-Complete Feature (BURST-COMPLETE Field in SMS_CLASS_ARBITER0,
SMS_CLASS_ARBITER1, and SMS_CLASS_ARBITER2)
A burst request can be submitted to the arbitration either as soon as the first request of the burst is
received by the SMS or when at least one complete burst is buffered into the FIFO. The behavior is
programmable on a per-group basis using the BURST-COMPLETE field of the
, and
registers. A per-FIFO counter tracks the number
of complete bursts in a FIFO.
10.2.4.1.2.3 ExtendedGrant Feature (EXTENDEDGRANT Field in SMS_CLASS_ARBITER0,
SMS_CLASS_ARBITER1, and SMS_CLASS_ARBITER2)
EXTENDEDGRANT is a programmable control field that allows a group to be granted for N consecutive
transactions (single or burst), assuming the group is still requesting service (FIFO is not empty).
EXTENDEDGRANT is applicable on a single/burst boundary. This multiple-service grant is intended to
take advantage of the high probability of two consecutive transactions within a group accessing
consecutive memory addresses (that is, in the same SDRAM page). This mechanism does not apply to
consecutive transactions that have been split by the RE. The maximum number of consecutive grants is
given in the EXTENDEDGRANT field of the
, and
registers. The allowed range is 1 to 3.
The ExtendedGrant logic is in the internal class arbitration but must be propagated to the interclass
arbitration. The flag qualifying a second-service request is provided to the interclass arbiter so the
extended grant scheme can be applied at the second level of arbitration.
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Class 0 requests can still override the ExtendedGrant scheme of class 1/class 2. Within an
ExtendedGrant window, hand-over to another class/thread (granting another thread) can occur as soon
as one idle cycle appears in the thread at burst or single boundary.
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The PWM counter of the interclass arbitration obeys the ExtendedGrant completion before handing
priority to the other class.
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When a split transaction from the RE is interleaved within an ExtendedGrant window, completion of the
ExtendedGrant window starts with the last ExtendedGrant counter value (not the initial value), because
there are two independent counters for ExtendedGrant and NOfServices. The ExtendedGrant counter
is reloaded to its programmed value when it reaches 0.
2239
SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
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