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SDRAM Controller (SDRC) Subsystem
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10.2.4.1.1 Memory Access Scheduling
NOTE: For a description of the SMS mode of operation and arbitration policy, see Section 10.2.6 ,
SDRC Use Cases and Tips.
The SMS includes a set of FIFOs to queue the requests received from the system interconnect or
processed by the RE. The FIFO entry contains a complete interconnect request, plus internal qualifiers
added by the RE which are required to correctly process the requests modified (or generated) by the RE.
The SMS also includes a response FIFO, which is shared by all response threads. This FIFO provides full
support for the response flow-control interconnect extension (handshake protocol).
When a memory transaction request arrives in the memory-access scheduler after being processed by the
VRFB module, the request is sent to one of eight FIFO queues.
The allocation to a particular queue is fixed and depends on the source of the request. To prioritize
concurrent transactions and optimize memory usage, each FIFO queue (and hence the memory-access
request source) is categorized into one of these three arbitration classes:
• Class 0 (highest priority): For bandwidth-sensitive devices with severe real-time constraints. The
system fails when the bandwidth requirement is not met. DSS or video display cores, camera capture
cores belong to this category.
• Class 1: For latency-sensitive devices where system performance degrades severely when the
average memory-access latency increases. These initiators also generally have some significant
bandwidth requirements. All CPU cores are class 1 initiators.
• Class 2: For all other devices, possibly with high-bandwidth requirements but without being too
latency-sensitive. Associated initiators may also have significant requirements in terms of bandwidth,
but if the bandwidth budget requirement cannot be serviced, the system performance degrades, but
remains functional (the system does not fail). General-purpose system DMA, multimedia accelerators
(graphics, imaging, video) belong to this category.
The arbitration between Class 1 and Class 2 is programmable.
Table 10-98 shows the mapping of FIFO queues and memory-access request sources to arbitration
classes.
Table 10-98. Arbitration Class Allocation
Class FIFO Queue Source Device
0 6 D2D
7 Display and Camera subsystems
1 0 MPU subsystem (instruction and data access)
1 IVA2 subsystem (instruction, data access, and MMU)
2 2 IVA2 subsystem DMA (read and write), sDMA WR
3 SGX
4 USB (HS + FS), DAP
5 sDMA (read)
A 2-level arbitration scheme determines the FIFO queue from which the next memory transaction is
granted.
NOTE: In the register description, a group represents a FIFO queue of requests from the initiator.
10.2.4.1.2 Arbitration Policy
A 2-level arbitration scheme is implemented to grant access to the SDRC. The arbitration uses fully
combinatorial logic, and the granted request is clocked before being issued on the interface master port of
the SDRC.
2238 Memory Subsystem SWPU177N – December 2009 – Revised November 2010
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