Public Version
L3 Interconnect
www.ti.com
Table 9-51. Target Agent Common Register Summary
Register Name
Type
Register
TA_OCM_ROM
TA_MAD2D
Width (Bits)
Physical
Physical
Address
Address
R
64
0x6800 2C00
0x6800 3400
R
64
0x6800 2C18
0x6800 3418
RW
64
0x6800 2C20
0x6800 3420
R
64
0x6800 2C28
0x6800 3428
RW
64
0x6800 2C58
0x6800 3458
R
64
0x6800 2C60
0x6800 3460
Table 9-52. Target Agent Common Register Summary
Register Name
Type
Register
TA_IVA2.2
TA_SGX
Width (Bits)
Physical
Physical
Address
Address
R
64
0x6800 6000
0x6800 6400
R
64
0x6800 6018
0x6800 6418
RW
64
0x6800 6020
0x6800 6420
R
64
0x6800 6028
0x6800 6428
RW
64
0x6800 6058
0x6800 6458
R
64
0x6800 6060
0x6800 6460
Table 9-53. Target Agent Common Register Summary
Register Name
Type
Register
TA_L4_CORE
TA_L4_PER
TA_L4_EMU
Width (Bits)
Physical
Physical
Physical
Address
Address
Address
R
64
0x6800 6800
0x6800 6C00
0x6800 7000
R
64
0x6800 6818
0x6800 6C18
0x6800 7018
RW
64
0x6800 6820
0x6800 6C20
0x6800 7020
RW
64
0x6800 6828
0x6800 6C28
0x6800 7028
RW
64
0x6800 6858
0x6800 6C58
0x6800 7058
R
64
0x6800 6860
0x6800 6C60
0x6800 7060
9.2.5.2.1 L3 Target Agent (L3 TA) Registers Description
Table 9-54. L3_TA_COMPONENT
Address Offset
0x000
Physical Address
See
to
Description
Component register of target agent
Type
R
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CODE
REV
Bits
Field Name
Description
Type
Reset
63:32
Reserved
Reserved
R
0x00000000
31:16
CODE
Component Code
R
See
(1)
.
(1)
TI Internal Data
2036
Interconnect
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...