Texas Instruments OMAP36 Series, Техническое справочное руководство

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EXIT_HS_MODE_LATENCY
LP
LP
EXIT
HS
ENTER
HS
HS
PACKET
CLK
ON
TRAIL
TRAIL
CLK REQUEST
CLK READY
DATA REQUEST
DATA READY
CLK LANE
DATA LANE
DATA STATE
T
HS-TRAIL
T
HS-EXIT
T
CLK-POST
DDR_CLK_POST
T
CLK-TRAIL
T
HS-EXIT
CLK SIGNAL
T
HS-EOT
if enable
EoT
EXIT
HS
dss-326
Public Version
Display Subsystem Functional Description
www.ti.com
Table 7-31. LP to HS Timing Parameters (continued)
Timing Description Register
Time between the CLK lane request assertion and the DSI_CLK_TIMING [15:8]
DDR_CLK_PRE
data request assertion to switch the data lanes to HS DDR_CLK_PRE
Time to enter into HS mode. It is critical that
ENTER_HS_MODE_LATENCY = 1 + DIVROUNDUP
ENTER_HS_MODE_LATENCY DSI_VM_TIMING7 [31:16]
(2 * REG_TLPXBY2, 4) + DIVROUNDUP
(1)
ENTER_HS_MODE_LATENCY
(REG_THSPREPARE ,4) + DIVROUNDUP
(REG_THSPRPR_T 3, 4)
(2)
(1)
The formula for ENTER_HS_MODE_LATENCY timing is relevant only in video mode. It does not need to be programmed in
command mode.
(2)
The formula DIVROUNDUP(value, div) is equivalent to ROUNDUP(value/div).
7.4.3.2.2 Timing Parameters for an HS to LP Transaction
Figure 7-90 shows the timing requirement when switching the state of the data and clock lanes from HS to
LP. Table 7-32 lists the HS to LP timing parameters.
Figure 7-90. HS to LP Timing
1662 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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