Texas Instruments OMAP36 Series, Техническое справочное руководство

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Camera ISP Register Manual
Bits Field Name Description Type Reset
3 CSIB_LCM_IRQ CSI1/CCP2B receiver module - event on memory channel. R/W/1to 0
READS: Clr
0: Event is false
1: Event is true
WRITES
0: Status bit unchanged
1: Status bit reset
2 RESERVED Write 0s for future compatibility. Read returns 0. R/W/1to 0
Clr
1 CSI2C_IRQ CSI2C module event. R/W/1to 0
READS: Clr
0: Event is false
1: Event is true
WRITES
0: Status bit unchanged
1: Status bit reset
0 CSI2A_IRQ CSI2A receiver module event. R/W/1to 0
READS: Clr
0: Event is false
1: Event is true
WRITES
0: Status bit unchanged
1: Status bit reset
Table 6-91. Register Call Summary for Register ISP_IRQ0STATUS
Camera ISP Integration
• Camera ISP Interrupt Requests : [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22]
Camera ISP Basic Programming Model
• Camera ISP CCDC Interrupts : [23] [24] [25]
• Camera ISP Preview Events and Status Checking : [26] [27] [28]
• Camera ISP Resizer Events and Status Checking : [29] [30] [31]
• Camera ISP H3A Event and Status Checking : [32] [33] [34]
• Camera ISP Histogram Event and Status Checking : [35] [36] [37]
• Camera ISP Central-Resource SBL Event and Status Checking : [38] [39] [40] [41] [42]
• Camera ISP CBUFF Interrupts : [43] [44]
Camera ISP Register Manual
• Camera ISP Registers Summary : [45]
Table 6-92. ISP_IRQ1ENABLE
Address Offset 0x0000 0014
Physical Address Instance ISP
See Table 6-81
Description INTERRUPT ENABLE REGISTER TO DSP. IRQ1 STATUS LINE.
The same events are mapped in IRQ0. However, one event shall be mapped to only one target.
Type RW
1311 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
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