Texas Instruments OMAP36 Series, Техническое справочное руководство

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Camera ISP Functional Description
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There are two types of shutter mechanisms: mechanical and electronic. A mechanical shutter is used only
for high-resolution sensors. The three control signals (cam_global_reset, cam_shutter, and cam_strobe)
are useful with a mechanical shutter. High frame rates can be achieved only with an electronic shutter.
When an electronic shutter is used, none of the three control signals is used.
Mechanical shutter mechanism:
•
Reset: All pixels of the sensor are reset to their black value. When the sensor has a global reset
feature, the mechanical shutter can be open during reset.
• Integration: The light received by the sensor is transformed into electrical charges that are stored
inside pixels. At the end of the integration time, the shutter must be closed. Exposure time is defined
by the time between reset release and shutter close.
• Readout: The charges accumulated in pixels are converted to digital values that are sent to the camera
receiver.
Electronic rolling shutter mechanism (ERS):
• Each line of the sensor is reset separately and read after a fixed amount of time. Expose time is
defined by the time between reset and read.
6.4.5 Camera ISP Bridge-Lane Shifter
The bridge-lane shifter module contains a data-lane shifter and an optional bridge:
• The data-lane shifter routes data sent to physical pins to the proper inputs of the CCDC module. It is
controlled by the
ISP_CTRL [7:6] SHIFT register. Table 6-35 describes the different configurations.
Table 6-35. Camera ISP Bridge-Lane Shifter
Sensor Connected to Data Lane Shifter 0 Data Lane Shifter 1 Data Lane Shifter 2 Data Lane Shifter 3 Note
8 bits [7:0] 8 bits 6 bits 4 bits 2 bits
[9:2] 10 bits 8 bits 6 bits 4 bits
[11:4] 12 bits 10 bits 8 bits 6 bits
[13:6] 14 bits 12 bits 10 bits 8 bits CSI2 only
10 bits [9:0] 10 bits 8 bits 6 bits 4 bits
[11:2] 12 bits 10 bits 8 bits 6 bits
[13:4] 14 bits 12 bits 10 bits 8 bits CSI2 only
12 bits [11:0] 12 bits 10 bits 8 bits 6 bits
[13:2] 14 bits 12 bits 10 bits 8 bits CSI2 only
14 bits [13:0] 14 bits 12 bits 10 bits 8 bits CSI2 only
Blue shading means that the data is too wide for the Video processing hardware: use IVA2.2.
Green shading means that precision is increased for intermediate results.
Orange shading means that precision is reduced.
Unshaded cells imply normal precision.
• An optional bridge allows the packing of bytes into 16-bit words. When it is used, the maximum data
rate allowed is increased. The placement of 8-bit data inside 16-bit words is configurable through the
ISP_CTRL [3:2] PAR_BRIDGE register. This mode can be useful to transfer an YCbCr data stream or
compressed stream to memory at very high speed:
– A minimum line-blanking period of 2 pixels must be obeyed when the bridge is enabled.
– Some CCDC modules cannot work with the bridge. For details, see Figure 6-79 .
6.4.6 Camera ISP Video-Processing Front End
The video-processing front end (VPFE) comprises the CCDC and the lens-shading compensation.
1192 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
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