Texas Instruments MSP430G2755, Руководство пользователя

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MSP430G2955
MSP430G2855
MSP430G2755
www.ti.com SLAS800 – MARCH 2013
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), the
CPU goes into LPM4 immediately after power-up.
Table 5. Interrupt Sources, Flags, and Vectors
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
Power-Up PORIFG
External Reset RSTIFG
Watchdog Timer+ WDTIFG Reset 0FFFEh 31, highest
Flash key violation KEYV
(2)
PC out-of-range
(1)
NMI NMIIFG (non)-maskable
Oscillator fault OFIFG (non)-maskable 0FFFCh 30
Flash memory access violation ACCVIFG
(2) (3)
(non)-maskable
Timer0_B3 TB0CCR0 CCIFG
(4)
maskable 0FFFAh 29
Timer0_B3 TB0CCR2 TB0CCR1 CCIFG,
maskable 0FFF8h 28
TBIFG
(2) (4)
Compa CAIFG
(4)
maskable 0FFF6h 27
Watchdog Timer+ WDTIFG maskable 0FFF4h 26
Timer0_A3 TA0CCR0 CCIFG
(4)
maskable 0FFF2h 25
Timer0_A3 TA0CCR2 TA0CCR1 CCIFG,
maskable 0FFF0h 24
TAIFG
(5) (4)
USCI_A0 or USCI_B0 receive UCA0RXIFG, UCB0RXIFG
(2) (5)
maskable 0FFEEh 23
USCI_B0 I2C status
USCI_A0 or USCI_B0 transmit UCA0TXIFG, UCB0TXIFG
(2) (6)
maskable 0FFECh 22
USCI_B0 I2C receive or transmit
ADC10 ADC10IFG
(4)
maskable 0FFEAh 21
Reserved 0FFE8h 20
I/O Port P2 (up to eight flags) P2IFG.0 to P2IFG.7
(2) (4)
maskable 0FFE6h 19
I/O Port P1 (up to eight flags) P1IFG.0 to P1IFG.7
(2) (4)
maskable 0FFE4h 18
Timer1_A3 TA1CCR0 CCIFG
(4)
maskable 0FFE2h 17
Timer1_A3 TA1CCR2 TA1CCR1 CCIFG,
maskable 0FFE0h 16
TAIFG
(2) (4)
See
(7)
0FFDEh 15
See
(8)
0FFDEh to
14 to 0, lowest
0FFC0h
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4) Interrupt flags are located in the module.
(5) In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
(6) In UART or SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
(7) This location is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h)
disables the erasure of the flash if an invalid password is supplied.
(8) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
Copyright © 2013, Texas Instruments Incorporated
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