SDHS Registers
610
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Sigma-Delta High Speed (SDHS)
22.5.13 SDHSCTL4 Register (Offset = 18h) [reset = 0h]
SDHSCTL4 is shown in
and described in
Return to
SDHS Control Register 4
Figure 22-39. SDHSCTL4 Register
15
14
13
12
11
10
9
8
RESERVED
R-0h
7
6
5
4
3
2
1
0
RESERVED
SDHSON
R-0h
R/W-0h
Table 22-24. SDHSCTL4 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-1
RESERVED
R
0h
Reserved. Always reads as 0.
0
SDHSON
R/W
0h
Turn on the SDHS module. When SDHSCTL0.TRGSRC =0, SDHS
Power-up/down bit.
Note:
- When SDHSCTL0.AUTOSSDIS = 0 and SDHSCTL0.TRGSRC =0,
the SDHSON bit only powers up the SDHS, does not start sampling.
- When SDHSCTL0.AUTOSSDIS = 1 and SDHSCTL0.TRGSRC =0,
the SDHSON powers up the SDHS and starts sampling when the
SDHS is fully powered up.
- When SDHSCTL0.TRGSRC = 1, this bit is invalid.
Reset type: PUC
0h (R/W) = Power down the SDHS module
1h (R/W) = Power on the SDHS module