HSPLL Registers
487
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
High-Speed PLL (HSPLL)
20.6.4 HSPLLIMSC Register (Offset = 6h) [reset = 0h]
HSPLLIMSC is shown in
and described in
.
Return to
Interrupt Mask Register. Note: writing '1' enables the corresponding interrupt.
Figure 20-6. HSPLLIMSC Register
15
14
13
12
11
10
9
8
RESERVED
R-0h
7
6
5
4
3
2
1
0
RESERVED
PLLUNLOCK
R-0h
R/W-0h
Table 20-5. HSPLLIMSC Register Field Descriptions
Bit
Field
Type
Reset
Description
15-1
RESERVED
R
0h
Reserved
0
PLLUNLOCK
R/W
0h
PLL Unlock Interrupt Mask bit.
Reset type: PUC
0h (R/W) = PLL Unlock Interrupt is disabled
1h (R/W) = PLL Unlock Interrupt is enabled