Plaintext
Ciphertext
AES128/192/256
encrypt
Key
Initialization Vector
Plaintext
Ciphertext
AES128/192/256
encrypt
Key
Plaintext
Ciphertext
AES128/192/256
encrypt
Key
A
B
AES Accelerator Operation
410
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
AES256 Accelerator
14.2.11.2 Cipher Block Chaining (CBC) Mode
The cipher block chaining cipher mode always performs an XOR on the ciphertext of the previous block
with the current block. Therefore, the encryption of each block depends not only on the key but also on the
previous encryption.
14.2.11.2.1 CBC Encryption
For encryption, the initialization vector must be loaded by software (or by a separate DMA transfer) into
AESXIN before the DMA can be enabled to write the first 16 bytes of the plaintext into AESAXDIN
Figure 14-8. CBC Encryption
To implement the CBC encryption without CPU interaction, two DMA channels are needed. Static DMA
priorities must be enabled. The DMA triggers must be configured as level-sensitive triggers.
Table 14-5. AES and DMA Configuration for CBC Encryption
AES
CMEN
AES
CMx
AES
OPx
DMA_A
Triggered by 'AES trigger 0'
DMA_B
Triggered by 'AES trigger 1'
1
01
00
Read ciphertext from
AESADOUT
Write plaintext to AESAXDIN, which also triggers the next
encryption
The following pseudo code snippet shows the implementation of the CBC encryption in software:
CBC_Encryption(key, IV, plaintext, ciphertext, num_blocks)
// Pseudo Code
{
Reset AES Module (clears internal state memory):
AESSWRST= 1;
Configure AES for block cipher:
AESCMEN= 1; AESCMx= CBC; AESOPx= 00;
Write key into AESAKEY;
Write IV into AESAXIN; // Does not trigger encryption.
// Assumes that state is reset (=> XORing with Zeros).
Setup DMA:
DMA0: Triggered by AES trigger 0,
Source: AESADOUT,
Destination: ciphertext,
Size: num_blocks*8 words, Single Transfer mode
DMA1: Triggered by AES trigger 1,
Source: plaintext, Destination: AESAXDIN,
Size: num_blocks*8 words, Single Transfer mode
Start encryption:
AESBLKCNT= num_blocks;
End of encryption: DMA0IFG=1
}