Texas Instruments MSP430F643 Series, Руководство пользователя

Страница: 74 / 120

MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433
SLAS720D – AUGUST 2010 – REVISED DECEMBER 2015 www.ti.com
Table 6-24. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION REGISTER OFFSET
System control SYSCTL 00h
Bootloader configuration area SYSBSLC 02h
JTAG mailbox control SYSJMBC 06h
JTAG mailbox input 0 SYSJMBI0 08h
JTAG mailbox input 1 SYSJMBI1 0Ah
JTAG mailbox output 0 SYSJMBO0 0Ch
JTAG mailbox output 1 SYSJMBO1 0Eh
Bus error vector generator SYSBERRIV 18h
User NMI vector generator SYSUNIV 1Ah
System NMI vector generator SYSSNIV 1Ch
Reset vector generator SYSRSTIV 1Eh
Table 6-25. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION REGISTER OFFSET
Shared reference control REFCTL 00h
Table 6-26. Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P2: 01D0h)
REGISTER DESCRIPTION REGISTER OFFSET
Port mapping password PMAPPWD 00h
Port mapping control PMAPCTL 02h
Port P2.0 mapping P2MAP0 00h
Port P2.1 mapping P2MAP1 01h
Port P2.2 mapping P2MAP2 02h
Port P2.3 mapping P2MAP3 03h
Port P2.4 mapping P2MAP4 04h
Port P2.5 mapping P2MAP5 05h
Port P2.6 mapping P2MAP6 06h
Port P2.7 mapping P2MAP7 07h
Table 6-27. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION REGISTER OFFSET
Port P1 input P1IN 00h
Port P1 output P1OUT 02h
Port P1 direction P1DIR 04h
Port P1 pullup/pulldown enable P1REN 06h
Port P1 drive strength P1DS 08h
Port P1 selection P1SEL 0Ah
Port P1 interrupt vector word P1IV 0Eh
Port P1 interrupt edge select P1IES 18h
Port P1 interrupt enable P1IE 1Ah
Port P1 interrupt flag P1IFG 1Ch
Port P2 input P2IN 01h
Port P2 output P2OUT 03h
Port P2 direction P2DIR 05h
Port P2 pullup/pulldown enable P2REN 07h
74 Detailed Description
Copyright © 2010–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F6438 MSP430F6436 MSP430F6435 MSP430F6433