Texas Instruments MSP430F643 Series, Руководство пользователя

Страница: 38 / 120

SDA
SCL
t
HD,DAT
t
SU,DAT
t
HD,STA
t
HIGH
t
LOW
t
BUF
t
HD,STA
t
SU,STA
t
SP
t
SU,STO
MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433
SLAS720D – AUGUST 2010 – REVISED DECEMBER 2015 www.ti.com
5.34 USCI (I
2
C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-15 )
PARAMETER TEST CONDITIONS V
CC
MIN MAX UNIT
Internal: SMCLK, ACLK
f
USCI
USCI input clock frequency External: UCLK f
SYSTEM
MHz
Duty cycle = 50% ±10%
f
SCL
SCL clock frequency 2.2 V, 3 V 0 400 kHz
f
SCL
≤ 100 kHz 4.0
t
HD,STA
Hold time (repeated) START 2.2 V, 3 V µs
f
SCL
> 100 kHz 0.6
f
SCL
≤
100 kHz 4.7
t
SU,STA
Setup time for a repeated START 2.2 V, 3 V µs
f
SCL
> 100 kHz 0.6
t
HD,DAT
Data hold time 2.2 V, 3 V 0 ns
t
SU,DAT
Data setup time 2.2 V, 3 V 250 ns
f
SCL
≤ 100 kHz 4.0
t
SU,STO
Setup time for STOP 2.2 V, 3 V µs
f
SCL
> 100 kHz 0.6
2.2 V 50 600
Pulse duration of spikes suppressed by
t
SP
ns
input filter
3 V 50 600
Figure 5-15. I
2
C Mode Timing
38 Specifications
Copyright © 2010–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430F6438 MSP430F6436 MSP430F6435 MSP430F6433