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T D
3
C (nF) t (s) 0.5 10 (s) 175
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EVM Setup and Operation
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10 SLVUAY9 – November 2016
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Copyright © 2016, Texas Instruments Incorporated
Revision History
Figure 16. RESET Deasserting Due to SENSE Voltage Rising Above V
IT
, C
T
Tied to GND Through 100-pF
Capacitor
4.3 Reset Output (RESET )
All TPS3808G01-Q1 devices offer an active-low RESET signal. The EVM has a test point connected
directly to the RESET pin. The reset signal will be asserted low when MR is pulled low or when the
voltage on the SENSE pin falls below VIT. When the voltage on SENSE is higher than the threshold
voltage, and the MR pin is pulled high or floating, then the reset pins will remain deasserted.
4.4 Reset Period Programming (C
T
)
The TPS3808G01-Q1 device has three options for setting the RESET delay time: connect to VDD through
a resistor, left floating, or connect to GND through a capacitor. Connecting C
T
to VDD through a resistor
sets a fixed 300-ms typical delay time and the resistor must be in the range of 40 k Ω to 200 Ω . The EVM
offers the J3 jumper to connect C
T
to VDD through a 40.2-k Ω resistor. Leave C
T
floating for a fixed 20-ms
delay time. Connect C
T
to GND through a capacitor for a user-defined delay time from 1.25 ms to 10 s.
The capacitor should be ≥ 100pF to be recognized. Using Equation 2 , the user can set the delay time
between the range previously mentioned:
where
• C = capacitor value
• t
D
= desired delay time in seconds (2)
Revision History
DATE REVISION NOTES
December 2016 * Initial Release