Texas Instruments LP875761-Q1, Руководство пользователя

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6 Board Layout
This section describes the board layout of the LP875761Q1EVM. See the LP875761-Q1 data sheet for specific
PCB layout recommendations.
The board is constructed on a 4-layer PCB. using 55-µm copper on top and bottom layers to reduce resistance
and improve heat transfer.
Board stack-up is shown in Figure 6-1 . Figure 6-2 shows the top view of the entire board and Figure 6-3 through
Figure 6-8 show the component placement, layout, and 3D view close to the LP875761-Q1 device.
Figure 6-1. Board Stack-Up
The design utilizes dual side placement of the components. This allows placement of the inductors next to the
LP875761-Q1 device for reducing SW node area for improved efficiency and reduced EMI. SW nets have also
snubber components to reduce SW pin spiking and EMI. The input capacitors can be placed very close to the
LP875761-Q1 device, to bottom side, to keep parasitic inductances low, and there is also space for input filters
for further EMI reduction.
www.ti.com Board Layout
SNVU751 – OCTOBER 2020
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The LP875761Q1EVM Evaluation Module 21
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