Quick Setup Guide
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8
SNVU472A – October 2016 – Revised February 2017
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The LP8756xQ1EVM Evaluation Module
2.2
Power Supply Setup
To power up the EVM, one power supply is needed. For full-load testing of the LP8756xQ1EVM, a DC-
power supply capable of at least 10 A and 4 V is required. 5 A is suggested as a practical minimum for
partial load. The power supply is connected to the EVM using connector X1. The power supply and
cabling must present low impedance to the UUT; the length of power supply cables must be minimized.
Remote sense, using connector X3, can be used to compensate for voltage drops in the cabling.
With the power supply disconnected from the UUT, set the supply to 3.7 V DC and the current limit to 5 A
minimum. Set the power supply output OFF. Connect the power supply's positive terminal (+) to VIN and
negative terminal (–) to GND on UUT (X1 power-in terminal block). Check that jumpers on the boards are
set as shown in
Figure 1
(factory default jumper configuration).
Set power supply output ON, and then continue with the following steps. Note that following steps is only
an example. Register values, enable control, mode and multiphase status may differ depending on the
LP8756xQ1EVM configuration.
1. On Evaluation software GUI, click on Assert NRST (see
Figure 7
).
2. Click on either of the two Read Registers buttons. You should see ready message on green
background next to the Read Registers button (see
Figure 8
).
3. Check that Buck0 is enabled (see
Figure 9
).
4. Click on Assert EN1 (see
Figure 10
).
5. Click on either of the two Read Registers buttons.
6. In this example case the GUI indicates "Disabled" under "Mode" until EN1 is asserted. After EN1 is
asserted "Mode" is changed to "Enabled". In case BUCKx is enabled or disabled with bit instead of
ENx pin, the "Mode" can be checked by reading registers. GUI indicates also "Master" under
"Multiphase status" of Buck 0. Mode of other bucks are "Disabled" and Multiphase status is "Slave to
Buck0". The EVM is now ready for testing with default register settings loaded.
Figure 7. Assert nRST
