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SNAU219B – June 2017 – Revised March 2020

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Copyright © 2017–2020, Texas Instruments Incorporated

Bill of Materials

Appendix B

SNAU219B – June 2017 – Revised March 2020

Bill of Materials

Table 3. Bill of Materials

DESIGNATOR

DESCRIPTION

MANUFACTURER

PART NUMBER

QUANTITY

C1, C3, C9, C14, C15, C17, C30

CAP, CERM, 0.1 µF, 16 V, ±5%, X7R,

0603

AVX

0603YC104JAT2A

7

C1_LF

CAP, CERM, 390 pF, 50 V, ±5%,

C0G/NP0, 0603

Kemet

C0603C391J5GACTU

1

C2, C4, C8, C16

CAP, CERM, 10 µF, 10 V, ±10%, X5R,

0805

Kemet

C0805C106K8PACTU

4

C2_LF

CAP, CERM, 0.068 µF, 50 V, ±10%, X7R,

0603

MuRata

GRM188R71H683KA93D

1

C4_LF

CAP, CERM, 1800 pF, 50 V, ±5%,

C0G/NP0, 0603

MuRata

GRM1885C1H182JA01D

1

C5, C6, C7, C10, C11, C12

CAP, CERM, 0.01 µF, 16 V, ±10%, X7R,

0402

AT Ceramics

520L103KT16T

6

C18, C23, C24, C26, C27, C28, C29

CAP, CERM, 1 µF, 16 V, ±10%, X7R, 0603

TDK

C1608X7R1C105K080AC

7

C19, C20, C21, C22, C25

CAP, CERM, 10 µF, 10 V, ±20%, X5R,

0603

TDK

C1608X5R1A106M080AC

5

CE_TP, CSB_TP, GND_TP, MUXout_TP,

RampCLK_TP, RampDIR_TP, SCK_TP,

SDI_TP, SYNC_TP, SysRefReq_TP,

Vcc_TP, VccRF_TP, Vtune_TP

Test Point, Compact, White, TH

Keystone

5007

13

Cin_0

CAP, CERM, 10 µF, 25 V, ±10%, X5R,

0805

MuRata

GRM219R61E106KA12D

1

Cout0

CAP, CERM, 22 µF, 16 V, ±10%, X5R,

0805

TDK

C2012X5R1C226K125AC

1

Css

CAP, CERM, 3300 pF, 50 V, ±5%,

C0G/NP0, 0603

MuRata

GRM1885C1H332JA01D

1

D1

LED, Green, SMD

Lite-On

LTST-C190GKT

1

L1, L2

Inductor, Multilayer, Air Core, 18 nH, 0.3 A,

0.36

Ω

, SMD

MuRata

LQG15HS18NJ02D

2

L1_TPS

Inductor, Shielded, Composite, 2.2 µH, 3.7

A, 0.02

Ω

, SMD

Coilcraft

XFL4020-222MEB

1

MUXout_SW

Switch, SPST, Slide, Off-On, 2 Pos, 0.1 A,

20 V, SMD

CTS Electrocomponents

219-2MST

1

OSCinM, OSCinP, SYNC, SysRef, Vcc

Connector, SMT, End launch SMA 50 ohm

Emerson Network Power

Connectivity

142-0701-851

5

R1

RES, 330

Ω

, 5%, 0.1 W, 0603

Yageo America

RC0603JR-07330RL

1

R2

RES, 100 k, 5%, 0.1 W, 0603

Vishay-Dale

CRCW0603100KJNEA

1

R2_LF

RES, 68, 5%, 0.1 W, 0603

Vishay-Dale

CRCW060368R0JNEA

1

R3_LF, R12, R15, R24, R25, R26, R30,

R31, R34, R35, R36, R41, R42, R43, R44,

R45

RES, 0, 5%, 0.1 W, 0603

Vishay-Dale

CRCW06030000Z0EA

16

R4_LF

RES, 18, 5%, 0.1 W, 0603

Vishay-Dale

CRCW060318R0JNEA

1

R5, R7, R8, R9, R16, R19, R20, R22

RES, 12 k

Ω

, 5%, 0.1 W, 0603

Vishay-Dale

CRCW060312K0JNEA

8

R37, R38, R39, R40

RES, 50, 0.1%, 0.05 W, 0402

Vishay-Dale

FC0402E50R0BST1

4

Rfbb1

RES, 180 k, 0.1%, 0.1 W, 0603

Yageo America

RT0603BRD07180KL

1

Rfbt1

RES, 562 k, 1%, 0.1 W, 0603

Vishay-Dale

CRCW0603562KFKEA

1

RFoutAM, RFoutAP, RFoutBM, RFoutBP

JACK, SMA, 50

Ω

, Gold, Edge Mount

Johnson

142-0771-831

4

U1

High Performance, Wideband PLLatinum™

RF Synthesizer

Texas Instruments

LMX2595RHAR

1

uWire

Header (shrouded), 100 mil, 5x2, Gold

plated, SMD

FCI

52601-S10-8LF

1

Содержание LMX2595 EVM

Страница 1: ...in the LMX2595 can generate or repeat the SYSREF signal and is designed for clock high speed data converters The integrated jitter from the EVM measurements is less than 50 fs at 9 GHz carrier frequency By providing a SYNC signal the user can synchronize the output phase across multiple LMX2595 devices The LMX2595 can also generate a frequency ramp as demonstrated in this evaluation module With an...

Страница 2: ...ic 7 Appendix B Bill of Materials 8 Appendix C Board Layers Stack Up 9 Appendix D Changing Reference Oscillator and Setup 11 Appendix E Connecting Reference Pro 12 Appendix F Ramping Feature 14 Appendix G SYSREF Feature 15 Appendix H Enabling Onboard DC DC Buck Converter TPS62150 16 Appendix I Appendix J Using the VCO Doubler 17 Trademarks PLLATINUM is a trademark of Texas Instruments All other tr...

Страница 3: ...d Low Noise PLL With Integrated VCO 1 Evaluation Board Setup Figure 2 LMX2595EVM Setup 1 Power a Set power supply to 3 3 V with 600 mA current limit and connect to VCC SMA 2 Input Signal a Connect a clean 100 MHz clock source to the OSCinP SMA 3 Programming Interface Reference Pro will provide SPI interface to program LMX2595 a Connect USB cable from laptop or PC to USB port in Reference Pro This ...

Страница 4: ...UXout 4 SDI 5 Not Used 6 GND 7 RampCLK 8 SCK 9 SysRefReq 10 SYNC 2 1 Installing the Software 1 Download TICS Pro from the TI Website at www ti com tool TICSPRO SW 2 Install the software by following the wizard 3 Search for the LMX2595 In the menu bar search Select Device PLL VCO LMX2595 Figure 4 Search for LMX2595 on TICS Pro 4 You are now ready to use this software Verify that you can communicate...

Страница 5: ...nging LMX2595 to a Lock State 1 Load the default mode by clicking on Default configuration Default Mode xxxx xx xx 2 From the menu bar select USB communications Write All Registers to write all the registers to LMX2595 Figure 7 TICS Pro GUI LMX2595 Default Configuration 4 Loop Filter Configuration The parameters for the loop filters are Table 2 Current Loop Filter Configuration PARAMETER VALUE VCO...

Страница 6: ... Gain 15 mA Phase Detector Frequency MHz 200 MHz VCO Frequency Designed for 15 GHz but works over the whole frequency range Figure 8 Loop Filter Configuration For detailed design and simulation of TI s PLLATINUM integrated circuits see the PLLatinum Sim Tool For application notes blogs or videos on TI PLL products see http www ti com pll 5 Key Results to Expect Figure 9 Phase Noise Plot at 14 GHz ...

Страница 7: ...AU219B June 2017 Revised March 2020 Submit Documentation Feedback Copyright 2017 2020 Texas Instruments Incorporated Schematic Appendix A SNAU219B June 2017 Revised March 2020 Schematic Figure 10 Schematic ...

Страница 8: ...X5R1C226K125AC 1 Css CAP CERM 3300 pF 50 V 5 C0G NP0 0603 MuRata GRM1885C1H332JA01D 1 D1 LED Green SMD Lite On LTST C190GKT 1 L1 L2 Inductor Multilayer Air Core 18 nH 0 3 A 0 36 Ω SMD MuRata LQG15HS18NJ02D 2 L1_TPS Inductor Shielded Composite 2 2 µH 3 7 A 0 02 Ω SMD Coilcraft XFL4020 222MEB 1 MUXout_SW Switch SPST Slide Off On 2 Pos 0 1 A 20 V SMD CTS Electrocomponents 219 2MST 1 OSCinM OSCinP SYN...

Страница 9: ...l 9 SNAU219B June 2017 Revised March 2020 Submit Documentation Feedback Copyright 2017 2020 Texas Instruments Incorporated Board Layers Stack Up Appendix C SNAU219B June 2017 Revised March 2020 Board Layers Stack Up The top layer is 1 oz copper Figure 11 Board Layer Stack Up Figure 12 Top Layer ...

Страница 10: ... ti com 10 SNAU219B June 2017 Revised March 2020 Submit Documentation Feedback Copyright 2017 2020 Texas Instruments Incorporated Board Layers Stack Up Figure 13 GND Layer Figure 14 Power Layer Figure 15 Bottom Layer ...

Страница 11: ...llenge at 100 Hz offset 1 A noise source 10 dB down from the PLL noise will contribute to raise the noise by 0 4 dB Table 4 Reference Oscillator Requirements 100 MHz REFERENCE MINIMUM REQUIREMENTS FOR A 0 4 dB IMPACT ON PLL INBAND PN 1 Offset Hz 100 1k 10k 100k Noise level dBc Hz 139 149 159 164 There are different options to provide a reference oscillator to LMX2595 Use onboard oscillator enable ...

Страница 12: ...LMX2595EVM Setup With Reference Pro The LMK61PD0A2 has several control pins dedicated for output format control output frequency control and output enable control These control pins can be configured through the jumpers shown in Table 6 and Table 7 Jumpers FS1 FS0 OS and OE can be used to configure the corresponding control pin to either high or low state by strapping the center pin to VDD positio...

Страница 13: ... 50 Ω to VCC 2 V termination is required on receiver 2 100 Ω differential termination R31 is provided on Reference Pro PCB Removing the differential termination on the EVM is possible if the differential termination is available on the receiver Table 8 Output Termination Schemes OUTPUT FORMAT COUPLING COMPONENT VALUE LVPECL AC default EVM configuration R25 R28 0 Ω R26 R29 150 Ω C24 C25 0 01 µF R27...

Страница 14: ...edback Copyright 2017 2020 Texas Instruments Incorporated Ramping Feature Appendix F SNAU219B June 2017 Revised March 2020 Ramping Feature VCO is ramping from 12 to 12 125 GHz This can be set up on the ramp GUI tab Figure 18 Ramping Example Figure 19 Ramping Example ...

Страница 15: ...IN_IGNORE box is unchecked 2 Click the Toggle SysRefReq Pin box to initiate SYSREF Figure 20 SYSREF Example Table 9 SYSREF Modes MODE NAME DESCRIPTION TICS PRO SYS REF SETTINGS Master Continuos LMX2595 generates SysRef pulses as long as SysRefReq pin is held high Default mode See quick start instructions Master Pulse LMX2595 generates a finite number of pulses as long as the SysRefReq pin is held ...

Страница 16: ...NAU219B June 2017 Revised March 2020 Enabling Onboard DC DC Buck Converter TPS62150 Figure 21 Resistor Configuration to Enable DC DC 1 MUST SWITCH R35 to Rtps1 2 MUST SWITCH R34 to Rtps2 3 Populate Rtps 4 DC DC circuitry was optimized for efficiency for 5 to 8 V but a voltage of 3 3 V to 17 V can be applied to VCC SMA after resistor network is configured correctly from steps above ...

Страница 17: ...dback Copyright 2017 2020 Texas Instruments Incorporated Appendix J Using the VCO Doubler Appendix I SNAU219B June 2017 Revised March 2020 Appendix J Using the VCO Doubler Figure 22 VCO Frequency Doubler Setup in TICSPro Figure 23 18 GHz Phase Noise Using VCO Doubler ...

Страница 18: ...tion Feedback Copyright 2017 2020 Texas Instruments Incorporated Revision History Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from A Revision July 2019 to B Revision Page Changed VCO output from 19 GHz to 20 GHz 1 ...

Страница 19: ...Copyright 2017 2020 Texas Instruments Incorporated Revision History Changes from Original June 2017 to A Revision Page Added external reference clock in Figure 2 3 Changed to use external reference clock 3 Added PCB layout diagrams 9 Added diagrams for different reference clock input configuration 11 ...

Страница 20: ...o change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you will fully indemn...

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