EVM Configuration
4
SNAU253 – June 2020
Copyright © 2020, Texas Instruments Incorporated
LMK05318B EVM User's Guide
(1)
The input levels on these pins are sampled only during POR.
(2)
FINC and FDEC pin controls are only available when DCO mode and GPIO pin control are enabled by registers.
Table 2. Device Start-Up Modes
HW_SW_CTRL
(
1)
INPUT LEVEL
START-UP
MODE
MODE DESCRIPTION
JUMPER CONFIGURATION
0
I
2
C
(Soft pin mode)
Registers are initialized from EEPROM, and I
2
C interface is
enabled with slave address 11001xxb. Logic pins:
• SDA/SDI, SCL/SCK: I
2
C Data, I
2
C Clock
• GPIO0/SYNCN: Output Sync (active low)
• GPIO1/SCS
(1)
: I
2
C Address LSB Select (Low = 00b,
Float = 01b, High = 10b)
• GPIO2/SDO/FINC
(2)
: DPLL DCO Frequency Increment
(active high)
• STATUS1/FDEC
(2)
: DPLL DCO Frequency Decrement
(active high), or Status output
To select this mode, short pin
03 of J3.
Configure the jumpers for I2C
mode:
1.
For J4, short pin 01, pin 02
and leave other pins open.
2.
For J5 and J8, short pin
02.
Float
(V
IM
)
SPI
(Soft pin mode)
Registers are initialized from EEPROM, and SPI interface is
enabled. Logic pins:
• SDA/SDI, SCL/SCK: SPI Data In (SDI), SPI Clock (SCK)
• GPIO0/SYNCN: Output Sync (active low)
• GPIO1/SCS: SPI Chip Select (SCS)
• GPIO2/SDO/FINC: SPI Data Out (SDO)
To select this mode, short pin
02 of J3.
Configure the jumpers for SPI
mode:
1.
For J4, short pin 04, pin
05, pin 06, pin 07 and
leave other pins open.
1
ROM + I
2
C
(Hard pin
mode)
Registers are initialized from the ROM page selected by
GPIO pins, and I
2
C interface is enabled with the 7-bit slave
address of 0x64. Logic pins:
• SDA/SDI, SCL/SCK: I
2
C Data, I
2
C Clock
• GPIO[2:0]: ROM page select at POR
• After POR, GPIO2/SDO/FINC and STATUS1/FDEC pins
can function the same as for HW_SW_CTRL = 0 if
enabled by registers.
To select this mode, short pin
03 of J3. Configure jumpers J7,
J8 and J5 to set voltage levels
of GPIO0, GPIO1 and GPIO2.
NOTE:
To ensure proper start-up into SPI Mode, the HW_SW_CTRL, STATUS0, and
STATUS1/FDEC pins must all be floating or biased to V
IM
(0.8-V typical) before the PDN pin
is pulled high. These three pins momentarily operate as 3-level inputs and get sampled at
the low-to-high transition of PDN to determine the device start-up mode during POR. If any of
these pins are connected to a host device (MCU or FPGA), TI recommends using external
biasing resistors on each pin (10-k
Ω
pullup to 3.3 V with 3.3-k
Ω
pulldown to GND) to set the
inputs to VIM during POR. After power-up, the STATUS pins can operate as LVCMOS
outputs and overdrive the external resistor bias for normal status operation.
3
EVM Configuration
3.1
Power Supply
The LMK05318B has five core VDD supply pins that operate at 3.3 V ± 5% and six output VDDO supply
pins that operate at 1.8 V, 2.5 V, or 3.3 V ± 5%.
•
To use onboard LDO, short pins 1-2 of J10 and short pins 1-2 of J11. Then supply 5 V power source to
J35 or VIN1 of J13. The VDDO level can be set by J12 (short pin 01 = 1.8 V, short pin 02 = 2.5 V,
short pin 03 = 3.3 V).
•
To use external power supply, short pins 2-3 of J10 and short pins 2-3 of J11. Then supply 3.3 V to
J35 or VIN1 of J13, and supply 1.8 V, 2.5 V or 3.3 V to J37 or VIN2 of J13.
•
To power up or power down the onboard XO, short pins 1-2 or pins 2-3 of J9.
3.2
Logic Inputs and Outputs
See
to set voltage levels for GPIO pins.
