19. SCLKX_Y_HS: Set half step for the SYSREF output.
20. SCLKX_Y_ADLY_EN: Enable analog delay for the SYSREF clock path.
21. SCLKX_Y_ADLY: If enabled, set the analog delay for the SYSREF clock path.
22. SCLKX_Y_PD: Power down the SYSREF clock path.
23. SCLKX_Y_POL: If set, polarity of SYSREF output clock is inverted.
24. CLKoutY_SRC_MUX: Select device clock or SYSREF clock path for CLKoutY.
25. SCLKX_Y_DIS_MODE: Set the output state of output clock drivers for the SYSREF clock. For values of 1
and 2 works in conjunction with control on this list #14, SYSREF_GBL_PD.
26. CLKoutY_FMT: Set the clock output format for CLKoutY.
27. Clock output frequency for CLKoutX and CLKoutY.
2.1.2 TICS Pro Tips
Mousing over different controls will display a help prompt with the register address, the data bit location and
length, and a brief register description in the lower-left
Context
help pane.
You can set a register equal to 0 or uncheck a register’s checkbox to perform the same action. Similarly, setting
a register equal to 1 is the same as checking that register’s checkbox.
3 PLL Loop Filters and Loop Parameters
In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL’s purpose is to substitute
the phase noise of a low-noise oscillator (VCXO) for the phase noise of a dirty reference clock. The first PLL is
typically configured with a narrow loop bandwidth to minimize the impact of the reference clock phase noise. The
reference clock consequently serves only as a frequency reference rather than a phase reference.
The loop filters on the LMK04832SEPEVM evaluation board are set up using the approach above. The loop filter
for PLL1 has been configured for a narrow loop bandwidth (< 1 kHz). The specific loop bandwidth values depend
on the phase noise performance of the oscillator mounted on the board.
and
contain the
parameters for PLL1 and PLL2 for each oscillator option.
TI’s PLLatinum
™
Sim tool can be used to optimize PLL phase noise/jitter for given specifications. See
www.ti.com/tool/PLLATINUMSIM-SW
for more information.
3.1 PLL1 Loop Filter
Table 3-1. PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO
122.88 MHz VCXO PLL
Phase Margin
50˚
Kφ (Charge Pump)
450 µA
Loop Bandwidth
14 Hz
Phase Detector Freq
1.024 MHz
VCO Gain
2.5 kHz/V
Reference Clock Frequency
122.88 MHz
Output Frequency
122.88 MHz (To PLL 2)
Loop Filter Components
LF1_C1 (C31) = 100 nF
LF1_C2 (C14) = 680 nF
LF1_R2 (R44) = 39 kΩ
(1)
Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and N will change the loop bandwidth.
3.2 PLL2 Loop Filter
Table 3-2. Integrated VCO PLL
PARAMETER
LMK04832-SEP
UNIT
VCO0
VCO1
LF2_C1 (C12)
0.047
nF
LF2_C2 (C10)
3.9
nF
C3 (internal)
0.03
nF
C4 (internal)
0.01
nF
LF2_R2 (R41)
0.62
kΩ
R3 (internal)
0.2
kΩ
R4 (internal)
0.2
kΩ
Charge Pump Current, Kφ
3.2
mA
Quick Start
4
LMK04832SEPEVM User’s Guide
Copyright © 2022 Texas Instruments Incorporated
