Texas Instruments LMK04832SEPEVM Скачать руководство пользователя страница 20 | Manualshive

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Table 9-1. Bill of Materials (BOM) (continued)

Designator

Description

PartNumber

PackageReference

Manufacturer

U6

LDO Regulator Pos 1.21V
to 20V 1A 6-Pin(5+Tab)
SOT-223 Tube

TPS73801MDCQPSEP

SOT223-6

Texas Instruments

Y1

VCXO, CMOS 122.880
MHz, 3.3V, SMD

CVHD-950-122.880

CVHD-950-4

Crystek Corporation

Y3

Crystal, 24.000 MHz,
20pF, SMD

ECS-240-20-5PX-TR

Crystal, 11.4x4.3x3.8mm

ECS Inc.

Bill of Materials

20

LMK04832SEPEVM User’s Guide

SNAU282 – SEPTEMBER 2022

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Copyright © 2022 Texas Instruments Incorporated

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Содержание LMK04832SEPEVM

Страница 1: ...TICS Pro to Program the LMK04832 SEP 5 5 1 Start TICS Pro Application 5 5 2 Select Device 5 5 3 Program the Device 6 5 4 Restoring a Default Mode 7 5 5 Visual Confirmation of Frequency Lock 7 5 6 Enable Clock Outputs 7 6 Evaluation Board Inputs and Outputs 9 7 Recommended Test Equipment 12 8 Schematics 13 9 Bill of Materials 16 A USB2ANY Firmware Upgrade 21 B TICS Pro Usage 25 11 1 Communication S...

Страница 2: ...ion of the device functionality and performance specifications To quickly set up and operate the board with basic equipment refer to the quick start procedure below and test setup shown in Figure 2 1 1 Connect a voltage of 4 5 V to the VCC SMA connector or terminal block The LMK04832 SEP and onboard VCXO operate at 3 3 V provided by the onboard TPS73801 SEP LDO and LP5900 LDO respectively Evaluati...

Страница 3: ... 26 27 18 3 10 Figure 2 2 Clock Outputs Page Description Diagram 1 SYNC_DISX Prevent the divider from being reset by SYNC SYSREF path 2 DCLKX_Y_DIV Divide value for the device clock If set to 1 then DCLKX_Y_DCC DCC HS must 1 3 DDLYdX_EN Enable dynamic digital delay for this divider 4 DCLKX_Y_HSg_PD If clear glitchless half step adjustments are enabled 5 DCLKX_Y_HS Set half step for this divider DC...

Страница 4: ...e the impact of the reference clock phase noise The reference clock consequently serves only as a frequency reference rather than a phase reference The loop filters on the LMK04832SEPEVM evaluation board are set up using the approach above The loop filter for PLL1 has been configured for a narrow loop bandwidth 1 kHz The specific loop bandwidth values depend on the phase noise performance of the o...

Страница 5: ...8 MHz Figure 4 1 Selecting a Default Mode for the LMK04832 SEP Device 5 Using TICS Pro to Program the LMK04832 SEP This section will demonstrate how to use TICS Pro For more information on using TICS Pro refer to Appendix A TICS Pro is available for download at http www ti com tool ticspro sw Before proceeding be sure to follow the instructions in Section 2 to ensure proper hardware connections 5 ...

Страница 6: ... very convenient Figure 5 2 Loading the Device After the device is initially loaded TICS Pro will automatically program changed registers so it is not necessary to reload the device upon subsequent changes in the device configuration It is possible to disable this functionality by ensuring there is no checkmark by the Options AutoUpdate Using TICS Pro to Program the LMK04832 SEP www ti com 6 LMK04...

Страница 7: ...ut formats your hardware is configured for out of the factory To measure phase noise at one of the clock outputs for example CLKout0 1 Go to the Clock Outputs page Section 11 9 2 Uncheck CLKoutX_Y_PD in the Clock Output box to enable the channel 3 Set the following as needed a For Device Clock i DCLKX_Y_PD 0 in Clock Mode Select box ii Set Bypass Div DCLKX_Y_BYP or Clock Divider DCLK0_1_DIV as des...

Страница 8: ... ADT2 1T or a high quality Prodyn BIB 100G is recommended for differential to single ended conversion b For LVPECL i A balun can be used or ii One side of the LVPECL signal can be terminated with a 50 Ω load and the other side can be run single ended to the instrument c For HSDS i A balun like ADT2 1T or high quality Prodyn BIB 100G is recommended for differential to single ended conversion d For ...

Страница 9: ... 9 through the CLKoutX_FMT control All clock outputs are AC coupled to allow safe testing with RF test equipment If an output pair is programmed to LVCMOS each output can be independently configured normal inverted or off tri state Best performance EMI reduction is achieved by using a complementary output mode like Norm Inv TI does NOT recommend using Norm Norm or Inv Inv mode Not Populated CLKout...

Страница 10: ...Distribution with Fin0 or CLKin1 Fin1 Fin0 and CLKin1 Fin1 are shared for use as an RF Input for Clock Distribution mode or for an external VCO mode External Feedback Input FBCLKin for 0 Delay CLKin1 is shared for use as an external feedback clock input FBCLKin to PLL1 N or PLL2 N for 0 delay mode Refer to the LMK04832 SEP SNAS838 data sheet for more details on using 0 delay mode with the evaluati...

Страница 11: ...P10 J46 CMOS Input Output Programmable status I O pin By default set as an input pin for synchronize the clock outputs with a fixed and known phase relationship between each clock output selected for SYNC A SYNC event also causes the digital delay values to take effect SYNC SYSREF_REQ pin forces the SYSREF_MUX into SYSREF Continuous mode 0x03 when SYSREF_REQ_EN 1 SYNC SYSREF_REQ pin can hold outpu...

Страница 12: ...output clocks AC performance such as rise time or fall time propagation delay or skew TI suggests using a real time oscilloscope with 8 GHz analog input bandwidth with 50 Ω inputs To evaluate clock synchronization or phase alignment between multiple clock outputs TI recommends using phase matched 50 Ω cables to minimize external sources of skew or other errors distortion that may be introduced if ...

Страница 13: ... on the following schematic by searching for their reference designators Figure 8 1 Schematic LMK04832 SEP www ti com Schematics SNAU282 SEPTEMBER 2022 Submit Document Feedback LMK04832SEPEVM User s Guide 13 Copyright 2022 Texas Instruments Incorporated ...

Страница 14: ...re 8 2 Schematic Power Supply Figure 8 3 Schematic Digital Schematics www ti com 14 LMK04832SEPEVM User s Guide SNAU282 SEPTEMBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Страница 15: ...ematic Clock Outputs 1 of 2 Figure 8 5 Schematic Clock Outputs 2 of 2 www ti com Schematics SNAU282 SEPTEMBER 2022 Submit Document Feedback LMK04832SEPEVM User s Guide 15 Copyright 2022 Texas Instruments Incorporated ...

Страница 16: ...C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 CAP CERM 0 1 µF 10 V 10 X7R 0402 C0402C104K8RACTU 0402 Kemet C21 CAP CERM 100 pF 50 V 5 C0G NP0 0603 C0603C101J5GACTU 0603 Kemet C24 C28 CAP CERM 10 uF 10 V 10 X7R 0805 GCM21BR71A106KE22L 0805 MuRata C25 CAP CERM 2200 pF 50 V 10 X7R 0603 C0603C222K5RACTU 0603 Kemet C26 CAP CERM 82 pF 50 V 10...

Страница 17: ...3100 SMD 2 Leads Body 3 2x3mm Wurth Elektronik D5 LED Green SMD LTST C190GKT 1 6x0 8x0 8mm Lite On FB1 FB2 FB12 Ferrite Bead 120 ohm 100 MHz 0 5 A 0603 BLM18AG121SN1D 0603 MuRata FB4 FB5 FB6 FB7 FB8 FB9 FB10 FB11 Ferrite Bead 120 ohm 100 MHz 0 4 A 0402 MMZ1005Y121CT000 0402 TDK J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 Connector ...

Страница 18: ...Grade 0 0402 CRCW0402240RJNED 0402 Vishay Dale R41 RES 620 5 0 1 W AEC Q200 Grade 0 0603 CRCW0603620RJNEA 0603 Vishay Dale R44 RES 39 k 5 0 1 W AEC Q200 Grade 0 0603 CRCW060339K0JNEA 0603 Vishay Dale R45 R52 R54 R75 R88 R89 RES 33 5 0 1 W AEC Q200 Grade 0 0603 CRCW060333R0JNEA 0603 Vishay Dale R50 R59 R77 R80 RES 270 5 0 1 W AEC Q200 Grade 0 0603 CRCW0603270RJNEA 0603 Vishay Dale R55 RES 1 0 M 5 0...

Страница 19: ...ity TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 Test Point Miniature White TH 5002 White Miniature Testpoint Keystone U1 Space Grade Ultra Low Noise JESD204B Dual Loop Clock Jitter Cleaner LMK04832SPAPSEP TQFP64_PowerPAD Texas Instruments U2 25 MHz Mixed Signal Microcontroller with 128 KB Flash 8192 B SRAM and 63 GPIOs 40 to 85 degC 80 pin QFP PN Gree...

Страница 20: ...Tube TPS73801MDCQPSEP SOT223 6 Texas Instruments Y1 VCXO CMOS 122 880 MHz 3 3V SMD CVHD 950 122 880 CVHD 950 4 Crystek Corporation Y3 Crystal 24 000 MHz 20pF SMD ECS 240 20 5PX TR Crystal 11 4x4 3x3 8mm ECS Inc Bill of Materials www ti com 20 LMK04832SEPEVM User s Guide SNAU282 SEPTEMBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Страница 21: ...o complete the update 1 When the USB2ANY Firmware Requirement pop up window appears click OK to continue Figure A 1 Firmware Requirement 2 The Firmware Loader pop up window will load Disconnect the USB cable from the EVM Figure A 2 Firmware Loader 3 Press and hold the BSL button while you connect the USB2ANY cable www ti com USB2ANY Firmware Upgrade SNAU282 SEPTEMBER 2022 Submit Document Feedback ...

Страница 22: ...Figure A 3 BSL Button Location USB2ANY Firmware Upgrade www ti com 22 LMK04832SEPEVM User s Guide SNAU282 SEPTEMBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Страница 23: ...r Figure A 4 Update Firmware 5 Click Upgrade Firmware to start the firmware upgrade Click Close after the upgrade is complete Figure A 5 Firmware Update Complete www ti com USB2ANY Firmware Upgrade SNAU282 SEPTEMBER 2022 Submit Document Feedback LMK04832SEPEVM User s Guide 23 Copyright 2022 Texas Instruments Incorporated ...

Страница 24: ... to check the USB connection Make sure the USB Connected button is green Figure A 6 USB Communications USB2ANY Firmware Upgrade www ti com 24 LMK04832SEPEVM User s Guide SNAU282 SEPTEMBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Страница 25: ...on Setup window allows you to select the USB2ANY or DemoMode interface In case you plan to connect multiple evaluation boards to your PC and run multiple instances of the TICS Pro software the drop down box will allow you to select specific USB2ANY devices Press the Identify button to determine which USB2ANY is currently selected Devices used by other instances of TICS Pro will not display in this...

Страница 26: ...ols typically not included on one of the other dedicated pages Figure 11 2 TICS Pro User Controls Page TICS Pro Usage www ti com 26 LMK04832SEPEVM User s Guide SNAU282 SEPTEMBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Страница 27: ...he list of registers and displayed in the top right An individual register or field may be read back by entering the name into the bottom right and clicking the Read button Register maps may be exported but also imported The import format may simply be the address and register data in hex format as illustrated in the address value column one register to a line Note Use the Export Register Map opti...

Страница 28: ...lows the user to set high level usage profiles to allow the device to operate in dual loop single loop or distribution mode The bottom LMK04832 sub modes section allows further JESD204B configuration 0 delay configuration or clock input configuration which may apply for many of the LMK04832 modes of operation Figure 11 4 TICS Pro Set Modes Page TICS Pro Usage www ti com 28 LMK04832SEPEVM User s Gu...

Страница 29: ...eshold the input must be above approximately 200 MHz to lock otherwise PLL1 will enter holdover If holdover is not enabled PLL1 will be prevented from locking if the input frequency is less than the threshold frequency and LOS is enabled In addition to the above steps auto clock selection mode must be used to allow the LMK04832 to automatically switch to holdover when enabled clocks for auto switc...

Страница 30: ...by which the active CLKinX is selected and change the routing options for the CLKinX inputs You can also reset the PLL1 R or PLL2 N divider on this page Figure 11 6 TICS Pro CLKinX Control Page TICS Pro Usage www ti com 30 LMK04832SEPEVM User s Guide SNAU282 SEPTEMBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Страница 31: ...y red text will help guide the user through properly setting up 0 delay mode When using dual PLL mode the OSCin Source combo box can be set to External VCXO which links the OSCin frequency with the external VCXO frequency When using single PLL2 mode the OSCin Source combo box can be set to Independent to allow the OSCin frequency to be unlinked from the external VCXO frequency Figure 11 7 TICS Pro...

Страница 32: ...toolbar as SYNC Dividers Note To use SYNC or SYSREF ensure that SYNC_EN 1 To use SYSREF in continuous pulser or reclocked modes be sure SYSREF_PD 0 The SCLKX_Y_DIS_MODE bits allow the clock outputs to be disabled or set to a low state Values 1 and 2 are only conditionally set by the SYSREF_GBL_PD bit therefore it is possible to power up down several SYSREF outputs by programming only one register ...

Страница 33: ... SYSREF clocks or one of each The naming convention uses X_Y for controls which can impact both CLKoutX even clock and CLKoutY odd clock X for controls impacting only CLKoutX and Y for controls impacting only CLKoutY Figure 11 9 TICS Pro Clock Outputs Page www ti com TICS Pro Usage SNAU282 SEPTEMBER 2022 Submit Document Feedback LMK04832SEPEVM User s Guide 33 Copyright 2022 Texas Instruments Incor...

Страница 34: ...E field which allows the input or output mode of the pin to be defined The second is the _MUX field which when set for output controls what the pin will output Figure 11 10 TICS Pro Other Page TICS Pro Usage www ti com 34 LMK04832SEPEVM User s Guide SNAU282 SEPTEMBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Страница 35: ... user to program sequences of register programming or pin control Figure 11 11 TICS Pro Burst Mode Page www ti com TICS Pro Usage SNAU282 SEPTEMBER 2022 Submit Document Feedback LMK04832SEPEVM User s Guide 35 Copyright 2022 Texas Instruments Incorporated ...

Страница 36: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Страница 37: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Страница 38: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Страница 39: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Страница 40: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Страница 41: ...o change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you will fully indemn...

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