Texas Instruments LMH1208, Руководство пользователя

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1 2
3 4
5 6
1
l Q š} s/E
(Level H)
1 l
Q
š}
'E
(Level L)
GND
(Not Valid)
20 l
Q
š}
'E
(Level R)
Input Pin Input Pin
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Setup
5 SNAU205A – March 2017 – Revised August 2019
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LMH1297EVM Evaluation Board
5.1 Modes of Operation
The LMH1297EVM can be used in one of three modes:
1. Pin Mode (Default) – Provides general access to the LMH1297 signal integrity and I/O control settings
with IC pin-level logic.
2. SPI Mode – Provides full access to the LMH1297 signal integrity and control settings with MISO,
MOSI, SCK, and SSN pins.
3. SMBus Mode – Provides full access to the LMH1297 signal integrity and control settings with SDA,
SCL, and GND pins. ADDR0 and ADDR1 pins are used for SMBus address strap.
Using either SPI or SMBus mode, users have full access to all register controls in the LMH1297. For
convenience, the LMH1297EVM features an on-chip MSP430 that is configured as a USB2ANY interface
between LMH1297 and PC through the mini-USB port header on J31.
NOTE: Currently, the interface from PC to on-board MSP430 can only support SMBus
communication.
The external control pins on the LMH1297EVM are used to configure the default device settings. A 4-level
input scheme across the control pin interface increases the amount of control levels available to the
device with fewer physical pins. The channel settings and controls are configurable in pin mode for the
LMH1297 4-logic levels (L, R, F, H). The four logic levels correspond to the following voltages in
Table 2 .
Table 2. Description of 4-Level Voltage Inputs and Jumper Ties
LEVEL SETTING NOMINAL PIN VOLTAGE
H Tie 1 k Ω to VIN VIN – 0.04 V
F Float (Leave Pin Open) 2/3 × VIN
R Tie 20 k Ω to GND 1/3 × VIN
L Tie 1k Ω to GND 0.08 V
Typical 4-Level Input Thresholds:
• Internal Threshold between L and R = 0.2 × VIN
• Internal Threshold between R and F = 0.5 × VIN
• Internal Threshold between F and H = 0.8 × VIN
To set these 4-level voltage inputs, each input is controlled by a group of 6 jumper pins set in Figure 3 .
Figure 3. Jumper Orientation for User Configuration
Therefore, the following jumper positions allow access to each of the four logic levels:
LEVEL JUMPER TIES
H Pin 1-3
F Pin 3-4 (or no connect)
R Pin 4-6
L Pin 3-5