Board Layout
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SNVU526 – May 2016
Copyright © 2016, Texas Instruments Incorporated
LM53625xQEVM and LM53635xQEVM User's Guide
4
Board Layout
The LM53635xQEVM uses a four-layer PCB stack-up design. Top Layer 1 and Bottom Layer 4 are
implemented using 2 oz. copper for optimized heat transfer and dissipation. Mid Layer 2 and Mid Layer 3
utilize 1 oz. copper. Total PCB thickness is 61 mil (1.55 mm).
Figure 4. Four-Layer PCB Stack-Up
The overall EVM PCB board size dimension is 4000 mil × 3000 mil (101 mm × 76 mm) with a top surface
area of 76 cm
2
. All vias on the PCB are constructed using 8-mil drill thru-hole with 16-mil pad size.
to
shows the PCB Layout for each Cu Layer. Top Layer1 and Bottom Layer4 are
constructed using large filled Cu areas connected to GND. This is done to improve thermal performance
as well as improve overall EMI performance. Mid Layer 2 is constructed using a large GND plane as well.
The intention here is to minimize loop inductance by placing metal right under the Top Layer 1 traces
minimizing the cross section of current loops. Mid Layer 3 is mainly used to route non-critical signal traces
to the IC.
NOTE:
The PCB board layout is not fully optimized to use for final applications, but gives a good
starting point. The layout can be simplified and optimized by eliminating features included for
evaluation purposes such as measurement sense lines, jumper connections and features
unused in a particular application such as the feedback resistor divider for fixed voltage
options.