R7 x C10 =
0.03V
(4.5V
±
0.49V) x 1209 ns
= 16.2 x 10
-5
R7 x C10 =
'
V
(V
IN
- V
A
) x t
ON
R3 =
40
P
A
8.2A x 0.057
:
= 11.7 k
:
Output Ripple Control
www.ti.com
and the load current at current limit calculates to 5.35A at 4.5V, and 5.24A at 24V.
To change the current limit threshold the value for R5 should be chosen to achieve 50 mV to 100 mV
across it at current limit, staying within the practical limitations of power dissipation and physical size of the
resistor. A larger value for R5 reduces the effects of the current limit comparator offset, but at the expense
of higher power dissipation. After selecting the value for R5, calculate the value for R3 by rearranging
Equation 1 above. See the Applications Information section of the LM25085A data sheet for a procedure
to account for ripple current amplitude and tolerances when selecting the resistor for the ADJ pin.
B) Q1 R
DS(ON)
method – To configure the evaluation board to use the R
DS(ON)
of Q1 for current limit
detection, move the jumpers at both JP1 and JP2 from the A-B position to the B-C position. This change
connects the ADJ pin resistor (R3) and the ISEN pin across Q1. Since the sense resistance is now the
R
DS(ON)
of Q1, R3 must be changed. The data sheet for the Si7465 PFET lists the typical R
DS(ON)
as 51 m
Ω
at V
GS
= 10V, and 64 m
Ω
at V
GS
= 4.5V. Therefore, the R
DS(ON)
is estimated to be nominally 57 m
Ω
at V
GS
=
7.7V. To achieve the same nominal current limit threshold as above (8.2A), using Equation 6 in the data
sheet R3 calculates to:
(6)
The load current is equal to the current limit threshold minus half the current ripple amplitude. R3 can be
changed to set other current limit detection thresholds.
6
Output Ripple Control
The LM25085A requires a minimum of 25 mVp-p ripple at the FB pin, in phase with the switching
waveform at the SW node, for proper operation. On this evaluation board, the required ripple is generated
by R7, C9, and C10, allowing the ripple at V
OUT
to be kept to a minimum, as described in option A below.
Alternatively, the required ripple at the FB pin can be supplied from ripple generated at V
OUT
and passed
through the feedback resistors, as described in options B and C below, using one or two less external
components.
A) Minimum Output Ripple: This evaluation board is supplied configured for minimum ripple at V
OUT
by
using components R7, C9 and C10. The ripple voltage required by the FB pin is generated by R7 and C10
since the SW node switches from
≊
-1V to V
IN
, and the right end of C10 is a virtual ground. The values for
R7 and C10 are chosen to generate a 25-40 mVp-p triangle waveform at their junction. That triangle wave
is then coupled to the FB pin through C9. The following procedure is used to calculate values for R7, C9
and C10:
1) Calculate the voltage V
A
:
V
A
= V
OUT
- (V
SW
x (1 - (V
OUT
/V
IN(min)
)))
(7)
where V
SW
is the absolute value of the voltage at the SW node during the off-time, typically 0.5V to 1V
depending on the diode, and V
IN
is the minimum input voltage. Using a typical value of 0.65V for V
SW
, V
A
calculates to 0.49V. This is the approximate DC voltage at the R7/C10 junction, and is used in the next
equation.
2) Calculate the R7xC10 product:
(8)
where t
ON
is the maximum on-time (
≊
1209 ns), V
IN
is the minimum input voltage, and
Δ
V is the desired
ripple amplitude at the R7/C10 junction, 30 mVp-p for this example.
(9)
R7 and C10 are then chosen from standard value components to satisfy the above product. On this
evaluation board, C10 is set at 3300 pF. R7 calculate to be 49 k
Ω
, and a standard value 48.7 k
Ω
resistor
is used. C9 is chosen to be 0.01 µF, large compared to C10. The circuit as supplied on this EVB is shown
in
Figure 3
.
The output ripple, which ranges from
≊
20 mVp-p at V
IN
= 4.5V to
≊
33 mVp-p at V
IN
= 24V, is determined
primarily by the ESR of the output capacitance (C6), and the inductor’s ripple current. See
Figure 10
.
4
AN-1933 LM25085A Evaluation Board
SNVA384B – February 2009 – Revised April 2013
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