J721E EVM Hardware Architecture
51
SPRUIS4A – December 2019 – Revised May 2020
Copyright © 2019–2020, Texas Instruments Incorporated
Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
4.10 QSGMII Ethernet Interface
The SERDES0 SGMII2 signals of J721E SoC is interfaced to Quad SGMII PHY VSC8514XMK-11 on the
Quad Port Ethernet board through CP board, two stacked RJ45 connectors with integrated magnetics PN#
LPJG17512AONL used for external communication.
The VC8514 device includes three external PHY address pins, PHYADD [4:2] to allow control of multiple
PHY devices on a system board sharing a common management bus. These pins set the most significant
bits of the PHY address port map. The lower two bits of the address for each port are derived from the
physical address of the port (0 to 3) and the setting of the PHY address reversal bit in register 20E1, bit 9.
Reference clock to the PHY is generated from SERDES clock generator (CDCI2) on the CP board by
default. Optionally, clock generator on the Quad Port Ethernet board also can provide the clock to the
PHY with resistor option.
Table 27. Clock Source Selection
Clock Source
Install
Remove
From CP Board (Default)
R1, R2
R3, R4
From On board clock generator
R3, R4
R1, R2
Programming of the clock generator is done through I2C0 port of the SoC. I2C signals to the on board
clock generator is connected through an active switch and paths are disconnected by pulling the
CDCI_I2C_SEL signal low. Since, both on-board and CP board clock generators have the same I2C slave
address, the programming of these clock generators will need special attention. While programming on
board clock generator, the clock generator (CDCI2) on the common processor boards will need to be
under reset.
