background image

3 Operation

3.1 Quick Start Setup

Follow these procedures to set up and use one of the INA2191EVM panels. For these instructions, n is gain 
option 1, 2, 3, 4, or 5.

1. Choose the desired gain option by choosing the panel with the label showing the desired gain.
2. Choose the settings for the enable (EN1 and EN2) and reference (REF1 and REF2) pins using jumpers 

JA2n and JA1n for the enable pins and J5n and J6n for the reference pins.

3. Shorting an enable pin to the supply voltage (Vs) turns the device's corresponding channel on, while shorting 

the enable pin to ground turns this channel off.

4. Shorting the reference pin to ground biases the output of the corresponding channel to ground, while 

shorting the reference pin to Vs/2 pin biases the output of the corresponding channel to mid-supply. Note 
that the on-board Vs/2 voltage is available to easily bias the device with no extra source; however, it is 
best practice to drive the reference pin with a low-impedance voltage source and thus inserting a buffer in 
between Vs/2 and the reference pin will ensure performance according to device datasheet specifications.

5. Connect an external DC supply voltage (between 1.7 V and 5.5 V) to a VS test point. Connect the ground 

reference of that supply to a GND test point on the same panel.

6. Provide a differential input voltage signal across the input pins and ensure the common-mode voltage (V

CM

of this differential signal is within the operational V

CM

 rating of the device.

a. The differential signal should be supplied across the input pins by driving the signal across J1n and J2n 

for channel 1 or J3n and J4n for channel 2 on the EVM, as explained in 

Section 3.2

.

7. Check to make sure all grounds of the sources and EVM are common and connected with low-impedance 

connections.

3.2 Measurements

The user can either emulate the voltage developed across a sense resistor based on a given set of system 
conditions with the INA2191EVM, or connect the device inputs to an external shunt resistor. The user can also 
solder a surface-mount technology (SMT) shunt resistor across the Rs+ and Rs– pads, and these inputs can be 
connected in series with the external system and load.

Note the following where n is gain option 1, 2, 3, 4, or 5.

• Each device channel has its own pads for an optional shunt resistor

– Rs1n is shunt resistor for channel 1, while Rs2n is the shunt resistor for channel 2.
– When running current through Rs1 or Rs2, the user can connect the load and source to the shunt resistor 

using the quick-connect tabs J1n and J2n for Rs1n or J3n and J4n for Rs2n.

– All shunt resistors will be referred to as Rshunt.

• Each device channel has its own input pins with test points

– IN1+ and IN1– are the silkscreen markings for channel 1 input pins IN+1 and IN–1 respectively.
– IN2 + and IN2– are the silkscreen markings for channel 2 input pins IN+2 and IN–2 respectively.
– All input nodes will be referred to as IN+ and IN– or just as input pins.

• Input pins connect to shunt resistor pads for each channel on each gain variant panel

– Rs1+ and Rs1– are the same nets as IN1+ and IN1– respectively for channel 1.
– Rs2+ and Rs2– are the same nets as IN2+ and IN2– respectively for channel 2.
– The shunt resistor and input pin nodes become different once the input resistors (R3n, R4n, R5n, R6n) are 

increased to resistance greater than 0 Ω.

To configure a measurement evaluation without a shunt resistor, follow this procedure:

1. Connect a positive differential voltage across the device channel inputs from IN+ to IN– (or Rs1+ to Rs–) 

using J1n and J2n tabs for channel 1 and J3n and J4n tabs for channel 2.
a. For any unused channel, short the inputs and tie these inputs to ground or some other valid common-

mode voltage (V

CM

).

2. If the differential supply is floating, then connect a –0.1-V to 40-V V

CM

 to the inputs of the device channel. 

Connect the positive lead of the V

CM

 source to the IN– tab and V

CM

 source ground to a GND test point.

www.ti.com

Operation

SBOU254A – JANUARY 2021 – REVISED JUNE 2021

Submit Document Feedback

INA2191EVM

5

Copyright © 2021 Texas Instruments Incorporated

Содержание INA2191EVM

Страница 1: ...t INA2191 current shunt monitor in a variety of configurations Throughout this document the terms evaluation board evaluation module and EVM are synonymous with the INA2191EVM This document also inclu...

Страница 2: ...91EVM Schematic Gain A5 Panel 12 Figure 5 6 INA2191EVM Top Overlay 13 Figure 5 7 INA2191EVM Bottom Overlay 13 Figure 5 8 INA2191EVM Top Layer 14 Figure 5 9 INA2191EVM Bottom Layer 14 Figure 5 10 INA21...

Страница 3: ...48 A per channel at room temperature Table 1 1 INA2191 Gain Option Summary Product INA2191 Gain V V INA2191A1 25 INA2191A2 50 INA2191A3 100 INA2191A4 200 INA2191A5 500 1 1 EVM Kit Contents Table 1 2 s...

Страница 4: ...connections and pads to solder down optional circuitry 2 1 Features The INA2191EVM PCB provides the following features Evaluation of all gain options through identical scored panels Ease of access to...

Страница 5: ...e INA2191EVM or connect the device inputs to an external shunt resistor The user can also solder a surface mount technology SMT shunt resistor across the Rs and Rs pads and these inputs can be connect...

Страница 6: ...with the load and bus voltage sources while powered off WARNING Make sure that the equipment shunt resistor wires connectors and so on can support the amperage and power dissipation first before you m...

Страница 7: ...ly voltage Vs 2 that can be tied directly to the device s reference pins 4 4 U1n INA2191 U1n is the location for the INA2191An test device Consider these factors when selecting the appropriate device...

Страница 8: ...INA2191EVM PCB manufacturing 5 1 Schematics Figure 5 1 through Figure 5 5 show the schematics for the A pinout of the INA2191EVM PCB for all gain options Figure 5 1 INA2191EVM Schematic Gain A1 Panel...

Страница 9: ...NA2191EVM Schematic Gain A2 Panel www ti com Schematic PCB Layout and Bill of Materials SBOU254A JANUARY 2021 REVISED JUNE 2021 Submit Document Feedback INA2191EVM 9 Copyright 2021 Texas Instruments I...

Страница 10: ...NA2191EVM Schematic Gain A3 Panel Schematic PCB Layout and Bill of Materials www ti com 10 INA2191EVM SBOU254A JANUARY 2021 REVISED JUNE 2021 Submit Document Feedback Copyright 2021 Texas Instruments...

Страница 11: ...NA2191EVM Schematic Gain A4 Panel www ti com Schematic PCB Layout and Bill of Materials SBOU254A JANUARY 2021 REVISED JUNE 2021 Submit Document Feedback INA2191EVM 11 Copyright 2021 Texas Instruments...

Страница 12: ...NA2191EVM Schematic Gain A5 Panel Schematic PCB Layout and Bill of Materials www ti com 12 INA2191EVM SBOU254A JANUARY 2021 REVISED JUNE 2021 Submit Document Feedback Copyright 2021 Texas Instruments...

Страница 13: ...or the INA2191EVM Figure 5 6 INA2191EVM Top Overlay Figure 5 7 INA2191EVM Bottom Overlay www ti com Schematic PCB Layout and Bill of Materials SBOU254A JANUARY 2021 REVISED JUNE 2021 Submit Document F...

Страница 14: ...om Layer Figure 5 10 INA2191EVM Top Solder Figure 5 11 INA2191EVM Bottom Solder Schematic PCB Layout and Bill of Materials www ti com 14 INA2191EVM SBOU254A JANUARY 2021 REVISED JUNE 2021 Submit Docum...

Страница 15: ...Figure 5 14 INA2191EVM Bottom Layer for Single Panel Figure 5 15 INA2191EVM Top Solder for Single Panel www ti com Schematic PCB Layout and Bill of Materials SBOU254A JANUARY 2021 REVISED JUNE 2021 Su...

Страница 16: ...ngle Panel Figure 5 17 INA2191EVM Drill Drawing for Single Panel Schematic PCB Layout and Bill of Materials www ti com 16 INA2191EVM SBOU254A JANUARY 2021 REVISED JUNE 2021 Submit Document Feedback Co...

Страница 17: ...TR Keystone J51 J52 J53 J54 J55 J61 J62 J63 J64 J65 JA11 JA12 JA13 JA14 JA15 JA21 JA22 JA23 JA24 JA25 20 Header 100mil 3x1 Gold TH PBC03SAAN PBC03SAAN Sullins Connector Solutions J71 J72 J73 J74 J75 5...

Страница 18: ...INA2191A2IYBJ Texas Instruments U13 1 Low Power Zero Drift Wide Dynamic Range Precision Current Sense Amplifier DSBGA12 INA2191A3IYBJ Texas Instruments U14 1 Low Power Zero Drift Wide Dynamic Range P...

Страница 19: ...S82 S83 S84 S85 S91 S92 S93 S94 S95 SA11 SA12 SA13 SA14 SA15 SA21 SA22 SA23 SA24 SA25 SA31 SA32 SA33 SA34 SA35 SA41 SA42 SA43 SA44 SA45 SA51 SA52 SA53 SA54 SA55 SA61 SA62 SA63 SA64 SA65 SA71 SA72 SA7...

Страница 20: ...ers in the current version Changes from Revision January 2021 to Revision A June 2021 Page Removed preview notice for the INA2191 3 Revision History www ti com 20 INA2191EVM SBOU254A JANUARY 2021 REVI...

Страница 21: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Страница 22: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Страница 23: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Страница 24: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Страница 25: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Страница 26: ...are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and...

Отзывы: