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DPDCLK

DPDCLKC

SYNCDC

SYNCA
SYNCB

SYNCC

SYNCD

h(SYNCD)

h(SYNCA, -B, -C)

su(SYNCD)

su(SYNCA, -B, -C)

T0286-01

GC5328

SLWS218A – OCTOBER 2009 – REVISED OCTOBER 2009

www.ti.com

DPD CLOCK AND FAST SYNC SWITCHING CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

CLK(DPD)

DPD input clock frequency

100

200

MHz

Duty

CLK(DPD)

DPD input clock duty cycle

30%

70%

h(SYNCD)

Input hold time after DPDCLK

↑

See

(1)

0.2

su(SYNCD)

Input setup time after DPDCLK

↑

See

(1)

0.4

h(SYNCA, -B, -C)

Input hold time after DPDCLK

↑

su(SYNCA, -B, -C)

Input setup time after DPDCLK

↑

0.4

Jitter

CLK(DPD)

(2)

Cycle-to cycle jitter

–2.5%

2.5%

(1)

Controlled by design and process

(2)

Jitter is based on a period of (1/(DPDClk × 2)) (for BUC Interp 1 or 2); (1/( DPDClk × 3)) (for BUC Interp 1.5 or 3).

Figure 11. DPD Clock and Fast Sync Timing Specifications

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GC5328

Содержание GC5328

Страница 1: ...m DESCRIPTION The GC5328 is a lower power version of the GC5322 wideband digital predistortion transmit processor The GC5328 includes a digital upconverter DUC block a crest factor reduction CFR block a digital predistortion DPD block feedback FB block and capture buffer CB blocks The GC5328 GPP block receives the interleaved IQ data from the baseband input The individual IQ channels are gain adju...

Страница 2: ...ex The CFR peak reduced output is routed to the Farrow resampler The Farrow resampler resamples the CFR output to the DPD clock rate The Farrow resampler block also has a complex mixer for composite carrier frequency offset The DPD subsystem has a circular limiter nonlinear DPD correction and a transmit equalizer The DPD correction can reduce the follow on circuitry distortion products The DPD out...

Страница 3: ...performance levels and maintain target PA performance levels By including the GC5328 in their system architecture manufacturers of BTS equipment can realize significant savings on power amplifier bill of materials BOM and overall operational costs due to the PA efficiency improvement The GC5328 meets multicarrier 3G performance standards PCDE composite EVM and ACLR at PAR levels down to 6 5 dB and...

Страница 4: ...NVERTERS DUCs The GC5328 DUC block has interpolation filters programmable delays and complex mixers for each channel There are two DUC blocks within the GC5328 The sum chain after the DUC channel combines the DUC channel streams or the bypass stream and sends the data to the CFR block Each DUC can operate in one wide two medium or six CDMA channels Each DUC has a PFIR for spectral shaping a CFIR f...

Страница 5: ... memory effects The circular hard limiter provides a circular clipper that limits the magnitude squared value to 6 dbFS This is optimized for hardware and for the allowed gain expansion in the nonlinear DPD correction The DPD has an RMS power meter and a peak I or Q monitor The predistortion is performed for the nonlinear correction in the DPD section The linear correction is performed in the Tx e...

Страница 6: ...1 2 DPD Clock DataClock TX DACI See HW Data Sheet Single Ended 1 8 V CMOS Single Ended 1 8 V CMOS DACB 15 0 TX DACQ See HW Data Sheet GC5328 SLWS218A OCTOBER 2009 REVISED OCTOBER 2009 www ti com 1 ExtTerm see DAC data sheet 2 ExtPullup 500 Ω to 1 8 V only required when DAC Data Clock 337 MHz Figure 4 GC5328 to DAC5682Z Interface 1 ExtTerm see DAC data sheet 2 ExtTerm1 tester uses 50 Ω to 0 9 V for...

Страница 7: ...d connections for shared feedback path operation see GC5325 schematic User s Guide in References The GC5328 simplifies timing by providing a FIFO for each ADC port NOTE There are eight LVDS data lanes and 1 LVDS clock lane If the ADC has 8 LVDS data lanes the MSB of the ADC is connected to LVDS lane 7 MSB of the A feedback port Figure 6 LVDS DDR ADC to GC5328 FB Interface MICROPROCESSOR MPU INTERF...

Страница 8: ... error output Testbus 15 0 Standard capture mode The capture buffers can be armed to collect the 4K complex samples after a programmable delay following a sync event Smart capture mode There are two trigger conditions that combine the number of samples greater than a threshold these are used to find a number of peak events while the transmit signal is above a threshold In this case the magnitude a...

Страница 9: ...k equalizer LUTs etc Feedback path tuner alignment Capturing and sourcing of data through SCBs NOTE The sync A external synchronization should match the customer Tx frame total Tx period i e 5 ms See the baseband interface figure these synchronization signals must meet the timing of the BBClk POWER METERS AND PEAK I or Q MONITORS There are three integrated I2 Q2 power meters in the GC5328 GPP each...

Страница 10: ... DATA0 UP DATA1 UP DATA2 VDD VDD SHV VDD SHV VDD VSS VSS VSS VSS1 VSS VSS1 VSS VSS VDD VDD SHV VDD SHV VDD VDD SHV MFIO 15 MFIO 14 K RDB CEB OEB VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS1 VSS VSS VDD VDD VDD VDD MFIO 13 MFIO 12 MFIO 11 J UP ADDR WRB VDD SHV VDD VDD1 VDD VDD VSS VSS VSS VSS VSS VSS1 VSS VSS VDD VDD VDD VDD MFIO 10 MFIO 9 MFIO 8 H UP ADDR UP ADDR UP ADDR VDD VDD VDD VDD VSS VSS VSS VS...

Страница 11: ...W2 W1 V21 V20 V3 V2 T15 T14 T13 T12 T11 T10 T9 T8 R15 R14 R13 R12 R11 R10 R9 R8 P15 P14 P13 P12 P11 P10 P9 P8 N15 N14 N13 N12 N11 N10 N9 N8 M22 M21 M15 M14 M13 M12 M11 M10 M9 M8 L15 L14 L13 L12 L11 L10 L9 L8 K15 K14 K13 K12 K11 K10 K9 K8 J15 J14 J13 J12 J11 J10 J9 J8 H15 H14 H13 H12 H11 H10 H9 H8 G15 G14 G13 G12 G11 G10 G9 G8 E22 E21 E20 E3 E2 E1 D22 D21 D20 D14 D2 D1 C22 C21 C2 C1 B22 B21 B2 B1 A...

Страница 12: ...B8 AA8 Y8 W8 AB7 AA7 O Transmit to DAC s FB 35 30 B13 A13 D13 C13 B12 A12 I Feedback from ADC s FB 29 20 D12 C12 A11 B11 A10 B10 C10 D10 A9 B9 I Feedback from ADC s FB 19 10 C9 D9 A8 B8 A7 B7 C7 D7 A6 B6 I Feedback from ADC s FB 9 0 A5 B5 C5 D5 B4 A4 D4 C4 B3 A3 I Feedback from ADC s MFIO 33 0 V1 U3 U2 U1 I O Multifunction input output interface MFIO 29 20 T3 T2 T1 R2 R1 P3 P2 P1 N3 N2 I O Multifu...

Страница 13: ...TX35 TX32 O DAC negative output TX36 TX29 TX25 DAC 15 10 N TX11 TX7 TX3 TX1 TX5 TX9 O DAC negative output DAC 9 0 N TX13 TX17 TX22 TX26 TX30 TX34 TX33 O DAC negative output TX37 TX28 TX24 DACCLK TX21 O Clock to DAC DACCLKC TX20 O Complementary clock to DAC DACSYNCP TX14 O Positive output data sync DACSYNCN TX15 O Negative output data sync FB INPUT FROM LVDS ADC Figure 6 shows the ADC data and cloc...

Страница 14: ...eedback from PA output ADCB 7 0 N FB21 FB23 FB25 FB27 FB29 FB31 FB33 FB35 I ADC B negative feedback from PA output ADCBCLK FB18 I Clock from ADC B ADCBCLKC FB19 I Complementary clock from ADC B MPU INTERFACE GUIDELINES The following section describes the hardware interface between the recommended microprocessor external memory and the GC5328 Users may select a microprocessor that meets their speci...

Страница 15: ...assed 2 5 kV HBM 500 V CDM 200 V MM Moisture sensitivity Class 3 floor life at 30 C 60 H 1 week Reflow conditions JEDEC standard 260 C Latchup JEDEC Level 2 per JEDEC 78 standard at 90 C and 1 5 Vmax 100 mA RECOMMENDED OPERATING CONDITIONS over operating free air temperature range unless otherwise noted MIN TYP MAX UNIT VDD VDDA2 VPP Core supply voltages Note VDDA2 VDD 1 14 1 2 1 26 V VDDA1 Analog...

Страница 16: ...characteristics for the baseband interface multifunction I O MFIO DPD clock and fast sync MPU and JTAG interfaces over recommended operating conditions Device is production tested at 90 C for the given specification and characterized at 40 C unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMOS INTERFACE VIL CMOS voltage input low 0 8 V VIH CMOS voltage input high 2 VDDSHV V VOL C...

Страница 17: ... TEST CONDITIONS MIN MAX UNIT BASEBAND INTERFACE fCLK BB Baseband input clock frequency GPP is ACTIVE 25 70 MHz GPP is BYPASSED 25 70 tsu BB Input data setup time before BBCLK BB 15 0 BBFR SYNCA SYNCB and SYNCC 1 3 ns MFIO18 19 th BB Input data hold time after BBCLK BB 15 0 BBFR MFIO18 19 1 5 ns th SYNCA B C Input data hold time after BBCLK Valid for SYNCA SYNCB and SYNCC 2 ns DutyCLK BB Duty cycl...

Страница 18: ...h SYNCD Input hold time after DPDCLK See 1 0 2 ns tsu SYNCD Input setup time after DPDCLK See 1 0 4 ns th SYNCA B C Input hold time after DPDCLK 2 ns tsu SYNCA B C Input setup time after DPDCLK 0 4 ns JitterCLK DPD 2 Cycle to cycle jitter 2 5 2 5 1 Controlled by design and process 2 Jitter is based on a period of 1 DPDClk 2 for BUC Interp 1 or 2 1 DPDClk 3 for BUC Interp 1 5 or 3 Figure 11 DPD Clo...

Страница 19: ...EB CEB setup time to RDB WRB is HIGH 7 ns tsu OEB OEB setup time to RDB WRB is HIGH 2 ns td RD DATA valid time after RDB WRB is HIGH 14 ns ADDR hold time to RDB WRB is HIGH 2 ns th RD OEB CEB hold time to RDB 0 tHIGH RD Time RDB must remain HIGH between READs WRB is HIGH 1 7 ns tZ RD DATA goes high impedance after OEB or RDB WRB is HIGH 1 7 ns 1 Controlled by design and process and not directly te...

Страница 20: ...OEB and RDB are HIGH 7 ns OEB setup time to WRB 2 DATA and ADDR hold time after WRB OEB and RDB are HIGH 2 th WR ns OEB and CEB hold time after WRB 0 tlow WR Time WRB and CEB must remain simultaneously LOW OEB and RDB are HIGH 15 ns thigh WR Time CEB or WRB must remain HIGH between WRITEs OEB and RDB are HIGH 10 ns Figure 13 MPU WRITE Timing Specifications 20 Submit Documentation Feedback Copyrigh...

Страница 21: ...TDI Input data hold time after TCK Valid for TDI and TMS 6 ns td TDO Output data delay from TCK 8 ns Figure 14 JTAG Timing Specifictions TX SWITCHING CHARACTERISTICS over operating free air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HSTL MODE DDR ex DAC5682 fCLK DAC DAC output clock frequency RL 100 Ω 1 300 MHz tSKW DAC DACCLK to DAC data RL 100 Ω 2 TBD ps ...

Страница 22: ...rate is limited to 200 MHz 2 td and tho data clock to data is measured during characterization Figure 16 TX Timing Specifications HSTL SDR ENVELOPE SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT MFIO CMOS SDR to Envelope Modulator fCLK ENV ENVELOPE data output clock frequency 2 mA load 1 DPDC MHz lk 2 td ENVCLK to E...

Страница 23: ...1 2 600 ps 8x2 DDR LVDS MODE ex ADS5545 ADS6149 fCLK ADCA ADCA interface clock frequency See 1 200 MHz tsu ADCA 2 P Input data setup time before CLK See 1 3 For port A 430 ps th ADCA 2 P Input data hold time after CLK See 1 3 For port A 260 ps fCLK ADCB ADCB interface clock frequency See 1 200 MHz tsu ADCB 2 P Input data setup time before CLK See 1 4 For port B 800 ps th ADCB 2 P Input data hold t...

Страница 24: ...ides the GC5328 input EVM Error vector magnitude FIR Finite impulse response type of digital filter I Q In phase and quadrature signal representation IF Intermediate frequency IIR Infinite impulse response type of digital filter JTAG Joint Test Action Group chip debug and test standard 1149 1 LO Local oscillator LSB Least significant bit Mb Megabits divide by 8 for megabytes MB MSB Most significan...

Страница 25: ...oHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants...

Страница 26: ......

Страница 27: ...ch statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications o...

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