Texas Instruments eZ-FET Emulation IP, Руководство пользователя

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Debug Probes Hardware and Software
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32 SLAU647L – July 2015 – Revised February 2018
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MSP Debuggers
5.7.3.2 Pin States After Power Up
Table 11 describes the electrical state of every JTAG pin after debug probe power up.
Table 11. MSP-FET430UIF Pin States
Pin Name After Power-Up
When JTAG Protocol is
Active
When Spy-Bi-Wire
Protocol is Active
1 TDO/TDI Hi-Z, pulled up to 3.3 V In, TDO In and Out, SBWTDIO
2 VCC_TOOL 3.3 V Target V
CC
Target V
CC
3 TDI/VPP Hi-Z, pulled up to 3.3 V Out, TDI Hi-Z, pulled up to V
CC
4 VCC_TARGET In, external V
CC
sense In, external V
CC
sense In, external V
CC
sense
5 TMS Hi-Z, pulled up to 3.3 V Out, TMS Hi-Z, pulled up to V
CC
6 N/C N/C N/C N/C
7 TCK Hi-Z, pulled up to 3.3 V Out, TCK Out, SBWTCK
8 TEST/VPP Out, Ground Out, TEST Hi-Z, pulled up to V
CC
9 GND Ground Ground Ground
10 N/C N/C N/C N/C
11 RST Out, V
CC
Out, RST Ground
12 N/C N/C N/C N/C
13 N/C N/C N/C N/C
14 N/C N/C N/C N/C