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SCPA033

8

PCI1520 Implementation Guide

6

Miscellaneous Pin Interface

6.1

Multifunction Terminals

The multifunction terminals (MFUNC6:0) can be programmed to serve many different roles using
the Multifunction Routing register at PCI configuration offset 8Ch. The discrete ISA interrupts
(IRQ15:2), INTA#, INTB#, and IRQSER are explained in Section 7 – Interrupt Configurations.
CLKRUN#, D3STAT#, and RI_OUT# are discussed in Section 9 – Power Management
Considerations. ZVSTAT, ZVSEL1#, and ZVSEL0# are used for ZV control. For more
information, please refer to the PCI1520 Data Manual.

LED_SKT, LEDA1, and LEDA2 can be used to indicate socket activity. When a PC Card is
being accessed, these outputs will be driven high. LED_SKT will be driven high for access to
either socket. LEDA1 and LEDA2 will only be driven high during access to their respective
socket.

GPE#, GPIx, and GPOx can be used to signal general purpose events to the system.

CAUDPWM provides a PWM output for the CAUDIO terminals (as opposed to the binary output
SPKROUT).

PCI LOCK# is an optional PCI signal as mentioned in Section 4 – PCI Bus Interface.

All unused multifunction terminals require a 43k

pullup resistor.

6.2

SPKROUT

SPKROUT is the output to the host system that can carry SPKR# or CAUDIO through the
PCI1520 from the PC Card interface. If SPKROUT is enabled for both sockets, it is driven as an
exclusive-OR of the two inputs. A 43k pulldown resistor is required to prevent oscillation when
SPKROUT is disabled and therefore tristated.

6.3

SUSPEND#

The assertion of SUSPEND# gates PRST#, GRST#, and PCLK from the PCI1520. More
information can be found in Section 9 – Power Management Considerations. A 43k

pullup

resistor is required on SUSPEND#. SUSPEND# cannot be low during boot.

Содержание DUAL SOCKET PC CARD CONTROLLER PCI1520 Implementation

Страница 1: ... and Parallel PCI Interrupts 9 7 3 Serial IRQ and Parallel PCI Interrupts 9 7 4 Serial IRQ and Serial PCI Interrupts 9 8 Software Considerations 10 8 1 EEPROM Configuration 10 8 2 BIOS Considerations 11 8 2 1 PCI Configuration Registers Standard 11 8 2 2 PCI Configuration Registers TI Extension 12 8 2 3 ExCA Compatibility Registers 12 8 2 4 CardBus Socket Registers 12 9 Power Management Considerat...

Страница 2: ...0 doc Initial Draft DGB 8 8 02 PCI1520 Implementation Guide 1 10 doc Added information about switchable pullup pulldown on CSTSCHG to Section 5 Corrected explanation of single socket implementation in Section 5 Added PCLK to list of SUSPEND gated signals in Section 6 3 Corrected bit number for INTRTIE in Section 7 Changed description of Cache Line Size Reg in Section 8 2 1 Removed duplicate Dev Cn...

Страница 3: ... power switch is the TPS2226A Other possibilities include the TPS2224A TPS2216A and the TPS2206 The TPS2223A is also available but does not provide 12V Vpp The EEPROM can be used to set various configuration registers but is not necessary if those registers are settable via software BIOS for the system IRQSER is used to pass both PCI interrupts and ISA style legacy interrupts to the system Only PC...

Страница 4: ...ut cannot be used to power other devices and is only available externally in order to provide a 1µF bypass capacitor VRPORT must have a 1µF bypass capacitor to ground in order for proper operation if the voltage regulator is enabled 2 2 Clamping Rails The PCI1520 has 3 clamping rails VCCP VCCA and VCCB VCCP is the PCI interface I O clamp rail and can be either 3 3V or 5V depending on the system im...

Страница 5: ...sockets When the PCI1520 receives a socket power request it sends the appropriate data across the P2 C interface CLOCK DATA and LATCH In turn the power switch turns on the appropriate levels for VCC and VPP for that socket A 2 7kΩ pulldown on LATCH is used to indicate to the PCI1520 that an EEPROM is being used to program the PCI1520 CLOCK can be provided either internally or externally depending ...

Страница 6: ...ault state The assertion of PRST does not initialize GRST only bits PRST also does not initialize PME context bits if PME in enabled More information can be found in Section 9 1 D3 Wake Information IDSEL should be resistively coupled 100Ω to one of the address lines between AD31 and AD11 Please refer to Section 3 2 2 3 5 System Generation of IDSEL and Section 4 2 6 footnote 31 Pinout Recommendatio...

Страница 7: ...t PC card is being used A damping resistor is necessary on the CCLK terminals between the PCI1520 and the PC Card sockets The value is system dependent If line impedance is in the range of 60 90Ω a 47Ω resistor is recommended For more information please see the PC Card Standard Revision 7 1 Section 5 3 2 1 4 CD line noise filtering is no longer required because the PCI1520 has an integrated digita...

Страница 8: ...and LEDA2 will only be driven high during access to their respective socket GPE GPIx and GPOx can be used to signal general purpose events to the system CAUDPWM provides a PWM output for the CAUDIO terminals as opposed to the binary output SPKROUT PCI LOCK is an optional PCI signal as mentioned in Section 4 PCI Bus Interface All unused multifunction terminals require a 43kΩ pullup resistor 6 2 SPK...

Страница 9: ...rupt configuration because many 16 bit PC Cards require legacy ISA interrupts and will not function properly 7 2 Parallel IRQ and Parallel PCI Interrupts The parallel IRQ and parallel PCI interrupts mode is selected by programming bits 2 1 to a value of 01b This allows interrupts to be routed through IRQ15 2 INTA and INTB This is not a recommended interrupt configuration because this requires all ...

Страница 10: ...driver which was compatible with a previous Texas Instruments CardBus controller such as the PCI1225 or PCI1420 or the Intel 82365SL should also be compatible with the PCI1520 8 1 EEPROM Configuration The following diagram represents the implementation of an EEPROM for the PCI1520 for configuration Figure 3 EEPROM Implementation On the rising edge of GRST if LATCH is low the Serial Bus Detect bit ...

Страница 11: ...0h Retry Status bits 7 6 PCI Retry CardBus Retry 12 0x00 91h Card Control bits 7 5 Ring Indicate Enable ZV Port Select 13 0x44 92h Dev Cntr bits 6 3 0 3V Capa IRQ serialized and parallel PCI 14 0x00 93h Diagnostic bits 7 4 0 15 0x00 a2h Power Management Capabilities bit 15 PME _Supp from D3cold 0 16 0x84 00h ExCA ID and Revision bits 7 0 17 0x00 Och CB Socket Force Event Function 0 bit 27 ZVSUPPOR...

Страница 12: ...stem Control Register PCI offset 80h This register contains many important system dependent variables Please refer to the datasheet for more details Of possible interest to the BIOS programmer SER_STEP INTRTIE P2CCLK MRBURSTDN MRBURSTUP and RIMUX Multifunction Routing Register PCI offset 8Ch This register controls the seven multifunction terminals of the PCI1520 This register must be set before th...

Страница 13: ...ment Interface Specification for PCI to CardBus Bridges a device returning to D0 from D3hot is required to assert an internal reset The PCI reset may or may not be asserted by the system However for a device returning to D0 from D3cold however PRST must be asserted by the system For a wake from D3cold the device needs to save its PME context in order for software to determine the source of the wak...

Страница 14: ...9 27 13 11 6 0 Multifunction routing register PCI offset 8Ch bits 27 0 Retry status register PCI offset 90h bits 7 5 3 1 Card control register PCI offset 91h bits 7 5 2 0 Device control register PCI offset 92h bits 7 5 3 0 Diagnostic register PCI offset 93h bits 7 0 Power management capabilities register PCI offset A2h bit 15 General purpose event status register PCI offset A8h bits 15 14 General ...

Страница 15: ...l register CardBus offset 10h bits 6 4 2 0 9 2 PME RI_OUT Behavior PME and RI_OUT are very important for power management The PME signal is useful for PCI power management systems The RI_OUT Ring Indicate Out signal is used for legacy power management systems PME and RI_OUT are multiplexed on the same pin The PCI1520 can also provide RI_OUT on the Multifunction terminals To enable passage of Ring ...

Страница 16: ...t will not power down and will remain powered This opens the possibility of potential card damage If a 3 3V card is inserted into the hot slot that was powered to 5V card damage will most likely occur It is therefore recommended that P2CCLK bit 27 at PCI offset 80h is set to a 1 so that the Internal Oscillator is enabled The CLOCK signal will then always be available as long as power is applied to...

Страница 17: ...core voltage or allow for an external 1 0µF bypass capacitor depending on the value of VR_EN A typical implementation would enable the regulator by grounding VR_EN and adding the bypass capacitor from VRPORT to ground For further details see the datasheet The PCI1520 does not have a VCCI pin Signals clamped to VCCI on the PCI1420 are clamped to VCCP on the PCI1520 A new power switch has been intro...

Страница 18: ... of the PCI Bus Power Management Specification Bit 4 AUX_PWR in the Power Management Capabilities register PCI offset A2h is now tied to bit 15 PME _Support for D3Cold D3_STAT functionality has been added to MFUNC5 MFUNC4 and MFUNC2 D3_STAT is asserted when PME is enabled and both functions are placed in D3 power state Bit 27 in the Socket Present State register Socket offset 08h now indicates Zoo...

Страница 19: ...herefore the PCI1520 no longer supports centralized or distributed DMA DMA was used by very few PC Cards most of which are obsolete DOS based sound cards DVD decoders A new standardized ZV register model has been implemented in the PCI1520 see datasheet for details The PCI1520 is backward compatible with the legacy ZV register model used in previous CardBus controllers The timing condition erratum...

Страница 20: ...eset must be asserted on a D3 to D0 transition For systems requiring wake from D3 GRST should be connected to a power on reset and PRST should be connected to the system PCI Reset When implementing GRST in this way it must be treated similar to PRST in that PCI Clock must be stable for 100µs before deassertion The sequence of events should be 1 Power on with GRST and PRST asserted 2 Clock becomes ...

Страница 21: ...trix have changed When MFUNC5 1001b it is now reserved instead of IRQ9 When MFUNC4 1111b it is now reserved instead of IRQ15 When MFUNC2 1011b it is now reserved instead of IRQ11 Bit 7 in the Device Control register PCI offset 92h is now SKTPWR_LOCK instead of RSVD This bit when set to 1b stops software from powering down the PC Card socket while in the D3 power state This may be necessary for wak...

Страница 22: ...PCI5V C BE 0 AD20 AD18 BVCC AD0 AD6 AD1 R12 43K 3 3VCC AVPP AD12 U3 TPS2226A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 5VIN 5VIN DATA CLOCK LATCH NC 12VIN AVPP AVCC AVCC AVCC GND NC RESET 3 3VIN 3 3VIN 3 3VIN OC NC BVCC BVCC BVCC BVPP 12VIN SHDN NC NC NC NC 5VIN AD25 AD21 GRST AD3 AD8 AD31 U2A PCI1520 PCI 1 2 3 4 5 6 7 8 9 10 11 12 13 208 207 206 205 204 203 ...

Страница 23: ... A_CREQ A_INPACK A_CAD22 A_A4 VR_OUT A_CAD21 A_A5 A_CRST A_RESET A_CAD20 A_A6 A_CVS2 A_VS2 A_CAD19 A_A25 A_CAD18 A_A7 A_CAD17 A_A24 A_CC BE2 A_A12 A_CFRAME A_A23 VCC A_CIRDY A_A15 A_CTRDY A_A22 A_CCLK A_A16 VCCA A_CDEVSEL A_A21 A_CGNT A_WE A_CSTOP A_A20 GND A_CPERR A_A14 A_CBLOCK A_A19 A_CPAR A_A13 A_RSVD A_A18 A_CC BE1 A_A8 A_A16 A_A22 B_D7 B_D7 B_A16 B_REG C3 1uF B_WE A_REG A_WE A_A23 A_CD2 BVCC...

Страница 24: ...eferences 1 PCI1520 GHK PDV PC Card Controllers Data Manual SCPS065A 2 PCI Local Bus Specification Revision 2 2 3 PC Card Standard Revision 7 1 4 PCI Bus Power Management Interface Specification Revision 1 1 5 PCI Mobile Design Guide Revision 1 0 ...

Страница 25: ...nt that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or end...

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