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Key Signal Synchronization
3-3
Support Functions
3.2
Key Signal Synchronization
The reset and power-down signals must be synchronized to MCLK before
being applied to any codec. As mentioned previously, RESET is generated by
the DSK or the user, and is asynchronous to the MCLK. Synchronization is
achieved by D-type flip-flop. Similarly, the PWDN signal is generated by the
user’s software, and is asynchronous to the MCLK signal. Synchronization of
PWDN is also achieved by D-type flip-flop.
Содержание DSP-Codec
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