Texas Instruments DS90UB953-Q1, Руководство пользователя

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Table 6-6. MIPI CSI-2 Output Signals - J2 Pinout (continued)
Pin # Signal Name Pin # Signal Name
31 CSI1_D0_N 32 VDD_3V3
33 CSI1_D1_P 34 VDD_3V3
35 CSI1_D1_N 36 VDD_3V3
37 NC 38 VDD_1V8
39 NC 40 VDD_1V8
Note
* Remove R7, R9, R11, R12, R15, R16, R17, R19, R21, R22, R25, R27, R31, R33, R35, R37, R40
and R42 for CSI-2 source connected to J1/J3 (Default) *
** Populate R7, R9, R11, R12, R15, R16, R17, R19, R21, R22, R25, R27, R31, R33, R35, R37, R40
and R42 when source connected through J2 **
6.4 FPD-Link III Signals
Table 6-7. FPD-Link III Signals
Reference Signal Description
CN1.1 RIN0+ Quad Mini-FAKRA connector
CN1.2 RIN1+ Quad Mini-FAKRA connector
CN1.3 RIN2+ Quad Mini-FAKRA connector
CN1.4 RIN3+ Quad Mini-FAKRA connector
6.5 I
2
C Interface
A standalone external I
2
C host can connect throughJ9, J10 for programming purposes. Examples of external I
2
C
host controllers are Texas Instruments USB2ANY and Total Phase Aardvark I
2
C/SPI host adapter (Total Phase
Part#: TP240141).
Optional access to I
2
C signals are also available throughCSI-2 connectors J1, J2, or J3. I
2
C signal levels can be
configured through J30 to be at 1.8V or 3.3V when the I
2
C interface is accessed through connectors J4, J5.
Table 6-8. IDx I
2
C Device Address Select - J34
Reference Signal Description
J7 IDX
Selects I
2
C Device Address
Open: 0x30 (7'b) or 0x60 (8'b)
Short: 0x3D (7'b) or 0x7A (8'b) (Default)
Table 6-9. Primary I
2
C Interface Header - J4
Reference Signal Description
J9.1 VDD_I2C External I
2
C bus voltage
J9.2 I2C_SCL I
2
C Clock Interface for primary I
2
C bus
J9.3 I2C_SDA I
2
C Data Interface for primary I
2
C bus
J9.4 GND Ground
Table 6-10. Secondary I
2
C Interface Header - J5
Reference Signal Description
J10.1 VDD_I2C External I
2
C bus voltage
J10.2 I2C_SCL2 I
2
C Clock Interface for secondary I
2
C bus
Board Connections www.ti.com
12 DS90UB960-Q1EVM User's Guide SNLU226B – FEBRUARY 2018 – REVISED APRIL 2021
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