Texas Instruments DS16EV5110, Руководство оператора

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DS16EV5110
www.ti.com SNLS249M – FEBRUARY 2007 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
(1)(2)
Symbol Parameter Conditions Min Typ Max Units
N Supply Noise Tolerance
(3)
DC to 50MHz 100 mV
P-P
CML INPUTS
V
TX
Input Voltage Swing (Launch Measured differentially at TPA
800 1200 mV
P-P
Amplitude) ( Figure 2 )
V
ICMDC
Input Common-Mode Voltage DC-Coupled Requirement
V
DD
-0.3 V
DD
-0.2 V
Measured at TPA ( Figure 2 )
V
IN
Input Voltage Swing Measured differentially at TPB
120 mV
P-P
( Figure 2 )
R
LI
Differential Input Return Loss 100 MHz– 825 MHz, with fixture's
10 dB
effect de-embedded
R
IN
Input Resistance IN+ to VDD and IN − to VDD 45 50 55 Ω
CML OUTPUTS
V
O
Output Voltage Swing Measured differentially with OUT+
and OUT
− terminated by 50 Ω to 800 1200 mV
P-P
VDD
V
OCM
Output common-mode Voltage Measured Single-ended V
DD
-0.3 V
DD
-0.2 V
t
R
, t
F
Transition Time 20% to 80% of differential output
voltage, measured within 1" from
75 240 ps
output pins.
t
CCSK
Inter Pair Channel-to-Channel Difference in 50% crossing
Skew (all 4 Channels) between shortest and longest 25 ps
channels
t
D
Latency 350 ps
OUTPUT JITTER
TJ1 Total Jitter at 1.65 Gbps 20m 28 AWG STP DVI Cable
Data Paths
0.13 0.17 UI
P-P
EQ Setting 0x04 PRBS7
(4) (5) (6)
TJ2 Total Jitter at 2.25 Gbps 20m 28 AWG STP DVI Cable
Data Paths
0.2 UI
P-P
EQ Setting 0x04 PRBS7
(4) (5) (6)
TJ3 Total Jitter at 165 MHz Clock Paths
0.165 UI
P-P
Clock Pattern
(4) (5) (6)
TJ4 Total Jitter at 225 MHz Clock Paths
0.165 UI
P-P
Clock Pattern
(4) (5) (6)
RJ Random Jitter See
(6) (7)
3 ps
rms
BIT RATE
F
CLK
Clock Frequency Clock Path
(4)
25 225 MHz
BR Bit Rate Data Path
(4)
0.25 2.25 Gbps
(3) Allowed supply noise (mV
P-P
sine wave) under typical conditions.
(4) Specification is ensured by characterization and is not tested in production.
(5) Deterministic jitter is measured at the differential outputs (TPC of Figure 2 ), minus the deterministic jitter before the test channel (TPA of
Figure 2 ). Random jitter is removed through the use of averaging or similar means.
(6) Total Jitter is defined as peak-to-peak deterministic jitter from
()
+ 14.2 times random jitter in ps
rms
.
(7) Random jitter contributed by the equalizer is defined as sq rt (J
OUT
2
−
J
IN
2
). J
OUT
is the random jitter at equalizer outputs in ps
rms
, see
TPC of Figure 2 ; J
IN
is the random jitter at the input of the equalizer in ps
rms
, see TPA of Figure 2 .
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