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2.5 DS160PR810 RX Detect State Machine
Each DS160PR810 deploys an RX Detect state machine that governs the RX detection cycle as defined in the
PCI Express specification. At power up or after a manually triggered event, the redriver determines whether or
not a valid PCI Express termination is present at the far end of the link. The RX_DET pin of DS160PR810
provides additional flexibility to system designers to appropriately set the device in their desired mode, according
to
Table 2-5 .
Table 2-5. Four-Level Control Pin Settings
PD PIN LEVEL RX_DET/SCL PIN LEVEL DESCRIPTION
L L0
PCI Express RX detection state machine is disabled. Recommended
for non-PCI Express use cases. Inputs are always 50 Ω.
L L1
PCI Express RX detection state machine is enabled. Recommended
for PCI Express use cases. Pre Detect: Hi-Z, Post Detect: 50 Ω.
Outputs poll every approximate 150 μs until 3 consecutive valid RX
termination detections.
L L2
PCI Express RX detection state machine is enabled. Recommended
for PCI Express use cases. Pre Detect: Hi-Z, Post Detect: 50 Ω.
Outputs poll every approximate 150 μs until 2 consecutive valid RX
termination detections.
L L3 (Float)
PCI Express RX detection state machine is enabled. Recommended
for PCI Express use cases. Pre Detect: Hi-Z, Post Detect: 50 Ω.
Outputs poll every approximate 150 μs until a valid RX termination
detection.
H X Manual reset, inputs are Hi-Z
2.6 DS160PR810 DC Gain Control
When operating in Pin Mode, the GAIN pins can be used to set the overall datapath DC (low frequency) gain of
the DS160PR810 as shown in
Table 2-6 .
Table 2-6. GAIN Control
GAIN/SDA PIN
LEVEL
GAIN SETTING
L0 –6 dB
L1 –3 dB
L2 3 dB
L3 0 dB (Recommended for most use cases)
The DC gain of each channel of each device can also be set by writing to SMBus, I2C registers in Slave or
Master Modes. Refer to the
DS160PR810 Programming Guide (SNLU268) for details.
Description www.ti.com
6 DS160PR810EVM-RSC Evaluation Module (EVM) SNLU273 – DECEMBER 2020
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