SNLS459 – APRIL 2011
The CAP DAC value can be overridden by writing new values to bits 4:0 of register 0x08 (for CAP DAC setting 1)
and bits 4:0 of 0x0b (for CAP DAC setting 2). The override bit, bit 7 of register 0x09 must be set for the override
CAP DAC values to take effect. Since the valid rate and subrate setting for 10 GbE and 1 GbE applies to multiple
data rates, there are two CAP DAC values for this rate. The first is in register 0x08, bits 4:0, and the second is in
register 0x0b, bits 4:0. The DS125RT410 will use the CAP DAC value in register 0x08 for the larger divide ratio
(8) associated with the selected rate and subrate to try and acquire lock. If it fails to acquire lock, it will use the
CAP DAC value in register 0x0b with the smaller divide ratio (higher VCO frequency) associated with the
selected rate and subrate (1). It will continue to try to acquire lock in this way until it either succeeds or the
override bit (bit 7 of register 0x09) is cleared.
Overriding the Output Multiplexer
Register 0x09, bit 5, Register 0x14, bits 7:6, and Register 0x1e, bits 7:5
By default, the DS125RT410 output for each channel will be as shown in
Table 8. Default Output Status Description
Input Signal Status
Channel Status
Output Status
Not Present
No Signal Detected
Muted
Present
Not Locked
Muted
Present
Locked
Retimed Data
This default behavior can be modified by register writes.
Register 0x1e, bits 7:5, contain the output multiplexer override value. The values of this three-bit field and the
corresponding meanings of each are shown in
Table 9. Output Multiplexer Override Settings
Bit Field Value
Output Multiplexer Setting
Comments
0x7
Mute
Default when no signal is present or when
the retimer is unlocked
0x6
N/A
Invalid Setting
0x5
10 MHz Clock
Internal 10 MHz clock
Clock frequency may not be precise
0x4
PRBS Generator
PRBS Generator must be enabled to output
PRBS sequence
0x3
VCO Q-Clock
Register 0x09, bit 4, and register 0x1e, bit 0,
must be set to enable the VCO Q-Clock
0x2
VCO I-Clock
0x1
Retimed Data
Default when the retimer is locked
0x0
Raw Data
If the output multiplexer is not overridden, that is, if bit 5 of register 0x09 is not set, then the value in register
0x1e, bits 7:5, controls the output produced when the retimer has a signal at its input, but is not locked to it. The
default value for this bit field, 0x7, causes the retimer output to mute when the retimer is not locked to an input
signal. Writing a value of 0x0 to this bit field, for example, will cause the retimer to output raw data when it is not
locked to its input signal.
Setting the override bit, bit 5 of register 0x09, will cause the retimer to output the value selected by the bit field in
register 0x1e, bits 7:5, even when the retimer is locked.
When no signal is present at the input to the selected channel of the DS125RT410 the signal detect circuitry will
power down the channel. This includes the output driver which is therefore muted when no signal is present at
the input. If you want to get an output when no signal is present at the input, for example to enable a free-
running PRBS sequence, the first step is to override the signal detect. In order to force the signal detect on, set
bit 7 and clear bit 6 of channel register 0x14. Even if there is no signal at the input to the channel, the channel
will be enabled. If the channel was disabled before, the current drain from the supply will increase by 100–150
mA depending upon the other channel settings in the device. This increased current drain indicates that the
channel is now enabled.
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Copyright © 2011, Texas Instruments Incorporated
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