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Texas Instruments DS125BR800EVM, Руководство пользователя

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Texas Instruments DS125BR800EVM Скачать руководство пользователя страница 13

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EVM Layout

8

EVM Layout

The following Figures show the DS125BR800EVM board layout. The EVM controls signal integrity
functions via a combination of switches and jumpers.

The DS125BR800 is very compact and low power. The QFN package offers an exposed thermal pad to
enhance electrical and thermal performance. This must be soldered to the copper landing on the PWB.

Figure 4. Top Assembly Layer

Figure 5. Bottom Assembly Layer

13

SNLU122 – November 2012

DS125BR800EVM Evaluation Kit

Submit Documentation Feedback

Copyright © 2012, Texas Instruments Incorporated

Содержание DS125BR800EVM

Страница 1: ...DS125BR800EVM User s Guide User s Guide Literature Number SNLU122 November 2012 ...

Страница 2: ...t and the output connections for this evaluation board Commercially available adaptor boards can be purchased to facilitate connection to cables or backplane interconnects Topic Page 1 Features 3 2 4 Level IO Control 5 3 Switch Connection Overview 6 4 Quick Start Guide 7 5 SMBus Slave Mode of the EQ VOD and De Emphasis level 10 6 Bill of Materials for DS125BR800EVM 11 7 Schematic for DS125BR800EVM...

Страница 3: ...able via pin selection EEPROM or SMBus interface Single supply operation VIN 3 3V 10 or VDD 2 5V 5 40 C to 85 C Operation 5 kV HBM ESD rating High speed signal flow thru pin out package 54 pin QFN 10 mm x 5 5 mm 0 5 mm pitch Applications FR 4 Backplane Traces and High Speed Cable Ordering Information EVM ID DEVICE ID DEVICE PACKAGE DS125BR800EVM DS125BR800SQE NOPB QFN 54 Figure 1 DS125BREVK REV 1 ...

Страница 4: ...res www ti com Figure 2 DS125BREVK REV 1 DS125BR401 DS125BR800 Bottom Assembly 4 DS125BR800EVM Evaluation Kit SNLU122 November 2012 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated ...

Страница 5: ...re used to set the input condition for the 4 level inputs SW1 SW2 SW3 SW5 SW6 SW8 SW9 There are 3 switches connected to an input signal pin Each switch when set to the ON position sets the pin to one of the 4 level setting The 6 pin switches are assigned similar to the 3 pin switches The only difference is 2 signal pins are connected and thus 6 5 4 is for the one signal pin and 3 2 1 is for anothe...

Страница 6: ...AD 1 0 SMBUS MODE AD 1 0 device address bits SD_TH Signal detect threshold level FLOAT Default level SW6 SD_TH and LPBK RES LPBK function for BR401 only FLOAT Normal operation VDD_SEL and VDD_SEL Enable or disable the internal 3 3V to 2 5V regulator SW7 RESET RESET Enable or disable the device LOW enable SW8 EQA 1 0 PIN MODE EQ control for channel A inputs INPUT_EN Enable or disable the internal 5...

Страница 7: ...ected to a scope Table 3 SMA Channel Connections A B Channels Input Channel Output Channel J1 IN_B2 J2 IN_B2 J9 OUT_B2 J10 OUT_B2 B Channels J3 IN_B3 J4 IN_B3 J11 OUT_B3 J12 OUT_B3 J5 IN_A0 J6 IN_A0 J13 OUT_A0 J14 OUT_A0 A Channels J7 IN_A1 J8 IN_A1 J15 OUT_A1 J16 OUT_A1 4 Set the control pins for normal operation SW7 RESET 0 enables the device set switch pin2 to the ON position SW9 INPUT_EN 1 50 ...

Страница 8: ...A 1 0 R R Level 6 Table 4 EQ Settings available with PIN MODE Level EQA B 1 0 SW1 EQB 1 0 or SW8 EQA 1 0 EQ dB 6 GHz 6 5 4 3 2 1 1 0 0 ON OFF OFF ON OFF OFF 3 1 2 0 R ON OFF OFF OFF ON OFF 6 7 3 0 F ON OFF OFF OFF OFF OFF 8 4 4 0 1 ON OFF OFF OFF OFF ON 9 1 5 R 0 OFF ON OFF ON OFF OFF 13 7 6 R R OFF ON OFF OFF ON OFF 16 2 7 R F OFF ON OFF OFF OFF OFF 15 9 8 R 1 OFF ON OFF OFF OFF ON 17 0 9 F 0 OFF...

Страница 9: ...able in PIN MODE Level EQA B 1 0 SW1 EQB 1 0 or SW8 EQA 1 0 GEN1 and GEN2 Inner Amplitude 6 5 4 3 2 1 DE dB VPP 1 0 0 ON OFF OFF ON OFF OFF 0 8 0 2 0 R ON OFF OFF OFF ON OFF 0 9 0 3 0 F ON OFF OFF OFF OFF OFF 0 6 3 5 4 0 1 ON OFF OFF OFF OFF ON 1 0 0 5 R 0 OFF ON OFF ON OFF OFF 0 7 3 5 6 R R OFF ON OFF OFF ON OFF 0 5 6 7 R F OFF ON OFF OFF OFF OFF 1 1 0 8 R 1 OFF ON OFF OFF OFF ON 0 7 3 5 9 F 0 OF...

Страница 10: ...gnals are connected Set SW3 pin1 thru pin6 switches to the OFF position so they do not connect to the SDA and SCL line Set the SW1 and SW5 for the AD 3 0 pins AD 3 0 0000 sets device slave address B0 hex Connect SDA SCL and GND to J17 Please refer to datasheet for register map for EQ VOD and DEM 10 DS125BR800EVM Evaluation Kit SNLU122 November 2012 Submit Documentation Feedback Copyright 2012 Texa...

Страница 11: ...WM6503 ND 22 28 4033 CONN HEADER 3POS 100 VERT GOLD 9 1 J18 3M5473 ND 4808 3004 CP SOCKET IC 8 POS 3 R1 R2 R3 R4 R8 R11 R13 R14 R16 R17 R19 R20 R22 R23 R25 R26 10 31 P1 00KLCT ND ERJ 2RKF1001X RES 1 00K 1 10W 1 0402 R28 R29 R31 R32 R34 R35 R37 R38 R40 R41 R43 R44 R46 R47 R49 11 1 R7 P220LCT ND ERJ 2RKF2200X RES 220 1 10W 1 0402 R12 R15 R18 R21 R24 R27 12 13 R30 R33 R36 P20 0KLCT ND ERJ 2RKF2002X R...

Страница 12: ...S125BR800EVM www ti com 7 Schematic for DS125BR800EVM Figure 3 DS125BR800EVM Schematic 12 DS125BR800EVM Evaluation Kit SNLU122 November 2012 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated ...

Страница 13: ...The DS125BR800 is very compact and low power The QFN package offers an exposed thermal pad to enhance electrical and thermal performance This must be soldered to the copper landing on the PWB Figure 4 Top Assembly Layer Figure 5 Bottom Assembly Layer 13 SNLU122 November 2012 DS125BR800EVM Evaluation Kit Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated ...

Страница 14: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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