M0/APHASE
nSLEEP
nFAULT
BDECAY
DIR/BPHASE
STEP/BENBL
CONFIG
M1
GND
AVREF
J3
ADECAY
nENBL /AENBL
BVREF
VDD
Block Diagram
3
SLVU701B – March 2012 – Revised July 2019
Copyright © 2012–2019, Texas Instruments Incorporated
DRV8834 Evaluation Module
2.1
Power Connectors
The DRV8834EVM offers access to VM (motor voltage) power rail via a terminal block (J1). A set of test
clips in parallel with the terminal block allows for the monitoring of the input power rail.
User must apply VM according to datasheet recommended parameters.
NOTE:
VDD for logic and microcontroller is derived from a provided 3.3-V regulator stepped down
from the VM input voltage.
2.2
Test Stakes
A 0.100 inch pitch header connector (J3) is used to provide access to every device signal in the event a
different microcontroller is to be employed. To disconnect the internal MSP430 microcontroller, simply
remove power to this resource by removing the shunt from the JP3 jumper.
Figure 1. J3 Connector
