Texas Instruments DRV8328 EVM Series, Руководство пользователя, Страница: 22 / 29

6.9 Connectors, Selectors, and Analog Control Interface
GND GND
TP25 TP26
GND GND
TP27
TP28
GND
GND
OUTC
OUTB
OUTA
GND GND
OUTC
OUTB
OUTA
25 kohm
R90
POT
GND
AVDD
POT
1 2 3
J15
VDSLVL_SEL
25 kohm
R92
AVDD
GND
TP30
EXT_VDSLVL TP29
GND
GND
VDSLVL
VDSLVL Select
POT select by default
General purpose pot for MCU
Motor Phase Connector
1
2
3
J12
MOTOR_OUT
35A rated
1
2
J13
VDS_DISABLE
100k
R87
GVDD
Valid VDSLVL range: 0.1V - 2.5V
7.5k
R89
POT Voltage range: 0V - 2.538V
GND
DT (Pin 27 DRV8328A/B)
10k
R91
DNP
DT
DT
1 2
J14
GND
DT = GND: t_Dead = 55 ns
All values typical
DT = 10 k < R88 < 390 k: t_Dead = linear between 100 ns - 2000 ns
500k
R88
DT = Floating: t_Dead = 160 ns (DRV8328B) or 55 ns (DRV8328A)
R88 [ohms] = (t_Dead [ns])*200 - 10000
2
1
3
S1
nSLEEP_SW
10.0k
R73
TP23
PVDD
3.3V
300mW
D11
GND
nSLEEP
nSLEEP switch
C36/R77 designed for ~10us nSLEEP reset pulse
MCU GPIO should be defaulted to input when R75 is populated
nSLEEP
nSLEEP is 65V compliant but LP is not
Ensure D11 is populated when LP is connected
2.2nF
100V
C36
10.0k
R77
GND
0
R75
DNP
2
1
3
S2
10.0k
R74
DRVOFF switch
TP24
DRVOFF
0
R76
GND
0
R80
3.3V
300mW
D12
GND
DRVOFF_SW DRVOFF
PVDD
10k
R37
Ensure D12 is populated when LP is connected
DNP R76/R37 if DRVOFF is controlled by LP output
TP34 TP35 TP36
Figure 6-10. Connectors, Selectors, and Analog Control Interface schematic
Schematics www.ti.com
22 DRV8328xEVM User's Guide SLVUCD3A – NOVEMBER 2021 – REVISED AUGUST 2022
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