Texas Instruments DRA76xP-ACD, Руководство пользователя, Страница: 30 / 38

SoC
Mux
J
B1
B2
Ethernet
Expansion
Connector
A1=B1 or A1=B2
A1
RGMII0, MDIO
RGMII0_RXC, _RXCTL, _RXD[3:0],
_TXD, _TXCTL, _TXD[3:0]
MDIO_MCLK, _D
VIP2, GPIO5
VIN4B_CLK, _VS, _HS, _D[7:0],
GPIO5[31:29],25,22
SN74CBTLV16212
RGMII0_RXC, _RXCTL, _RXD[3:0],
_TXC, TXCTL, _TXD[3:0],
MDIO_MCLK, _D, UART3_TXD,
UART3_RXD
Copyright © 2017, Texas Instruments Incorporated
Signal Multiplex Logic
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30 SPRUII5A – December 2017 – Revised November 2018
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Copyright © 2017–2018, Texas Instruments Incorporated
DRA77xP/DRA76xP-ACD CPU EVM Board
4.7 RGMII0/VIN4B Selection (Mux J)
Table 22 is part of the SoC pinmux table for RGMII0. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
include:
• Gig Ethernet (RGMII0): TXC, TXCTL, TXD[3:0], RXC, RXCTL, RXD[3:0]
• Management Data I/O (MDIO): MCLK, D
• Video Input Port (VIN4B): CLK, HSYNC, VSYNC, [7:0]
• General Purpose I/O (GPIO5): [31:29], 25, 22
Table 22. SoC Pinmux for RGMII0/VIN4B
Pad Name Function 1 Function 6 Function 15
rgmii0_rxc EMAC rgmii0_rxc VIP2 vin4b_d[5]
rgmii0_rxctl EMAC rgmii0_rxctl VIP2 vin4b_d[6]
rgmii0_rxd[0] EMAC rgmii0_rxd[0] GPIO5 gpio5_31
rgmii0_rxd[1] EMAC rgmii0_rxd[1] GPIO5 gpio5_30
rgmii0_rxd[2] EMAC rgmii0_rxd[2] GPIO5 gpio5_29
rgmii0_rxd[3] EMAC rgmii0_rxd[3] VIP2 vin4b_d[7]
rgmii0_txd[0] EMAC rgmii0_txd[0] GPIO5 gpio5_25
rgmii0_txd[1] EMAC rgmii0_txd[1] VIP2 vin4b_vsync1
rgmii0_txd[2] EMAC rgmii0_txd[2] VIP2 vin4b_hsync1
rgmii0_txd[3] EMAC rgmii0_txd[3] GPIO5 gpio5_22
rgmii0_txctl EMAC rgmii0_txctl VIP2 vin4b_d[4]
rgmii0_txc EMAC rgmii0_txc VIP2 vin4b_d[3]
mdio_mclk EMAC mdio_mclk VIP2 vin4b_clk1
mdio_d EMAC mdio_d VIP2 vin4b_d[0]
uart3_txd VIP2 vin4b_d[2]
uart3_rxd VIP2 vin4b_d[1]
Mux J: Selects between Gig Ethernet and Expansion. The selection is made using the IO expander #2, bit
P4, defaulting to Gig Ethernet.
Figure 13. Mux Diagram for RGMII0/VIN1B