Texas Instruments DRA76xP-ACD, Руководство пользователя, Страница: 24 / 38

SoC
GPMC_A[18:13]._CS[2]
Mux
A
QSPI1
QSPI1_SCLK, _D[3:0], _CS[0],
_RTCLK
GPMC
GPMC_A[18:13],_CS[2]
B1
B2
QSPI Memory
NOR Memory
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Signal Multiplex Logic
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24 SPRUII5A – December 2017 – Revised November 2018
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Copyright © 2017–2018, Texas Instruments Incorporated
DRA77xP/DRA76xP-ACD CPU EVM Board
4.1 GPMC/QSPI Selection (Mux A)
Table 16 is part of the SoC pinmux table for GPMC. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
include:
• Memory Bus (GPMC): A[18:13], CS[2]
• Quad Serial Bus (QSPI): SCLK, RTCLK, CS[0], D[3:0]
Table 16. SoC Pinmux for GPMC/QSPI
Pad Name Function 1 Function 2
gpmc_a[13] GPMC gpmc_a[13] QSPI1 qspi1_rtclk
gpmc_a[14] GPMC gpmc_a[14] QSPI1 qspi1_d[3]
gpmc_a[15] GPMC gpmc_a[15] QSPI1 qspi1_d[2]
gpmc_a[16] GPMC gpmc_a[16] QSPI1 qspi1_d[0]
gpmc_a[17] GPMC gpmc_a[17] QSPI1 qspi1_d[1]
gpmc_a[18] GPMC gpmc_a[18] QSPI1 qspi1_sclk
gpmc_cs[2 GPMC gpmc_cs[2] QSPI1 qspi1_cs[0]
Mux A: Selects between GPMC (NOR memory) and QSPI memory support.
NOTE: The mux is implemented using resistors. This is due to the signal rate and routing
restrictions of the QSPI interface. To enable the GPMC signals to NOR (shown in RED), the
board must be modified to move resistors.
Figure 7. Mux Diagram for GPMC/QSPI