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SoC
Mux
L
B1
B2
Expansion
DCAN2
Connector
A1
Copyright © 2017, Texas Instruments Incorporated
I2C3
I2C3_SDA, _SCL
DCAN2
DCAN2_TX,_RX
Displays
A1 = B1 or
Open
GPIO6_14, GPIO6_15
SN74CBTLV3257
1A=1B1 or 1A=1B2
Signal Multiplex Logic
32
SPRUII5A – December 2017 – Revised November 2018
Copyright © 2017–2018, Texas Instruments Incorporated
DRA77xP/DRA76xP-ACD CPU EVM Board
4.9
DCAN2/I2C3 Selection (Mux L)
is part of the SoC pinmux table for DCAN2. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
include:
•
Digital CAN Bus (DCAN2): TX, RX
•
I2C Serial Bus (I2C3): SCL, SDA
Table 24. SoC Pinmux for DCAN2
Pad Name
Function 3
Function 10
gpio6_14
DCAN2
dcan2_tx
I2C3
i2c3_sda
gpio6_15
DCAN2
dcan2_rx
I2C3
i2c3_scl
Mux L: Selects between DCAN2 to CAN/CAN-FD phy and I2C3 for display panel control. The selection is
made using the IO expander #2, bits P3, defaulting to I2C3. Additional control is provided by IO expander
#2 bit P5, when enables the DCAN2/I2C3 signals access to the expansion interface (default is no access).
Figure 15. Mux Diagram for DCAN2/I2C